Structure with isotropic silicon recess profile in nanoscale dimensions
a technology of isotropic silicon and nanoscale dimensions, applied in the direction of basic electric elements, electrical apparatus, semiconductor devices, etc., can solve the problems of difficult control of the etch rate of isotropic etch processes, limited amount of lateral etching relative to the depth of the trench formed by plasma etch, and difficulty in controlling the extent of vertical etching, etc., to achieve the effect of reducing the oxidation ra
Inactive Publication Date: 2012-08-02
GLOBALFOUNDRIES INC
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Benefits of technology
This approach allows for controlled nanoscale lateral etching, enabling the creation of non-planar interface regions and stress in semiconductor structures, which is crucial for advanced transistor designs, improving the precision and functionality of semiconductor devices.
Problems solved by technology
The etch rate of isotropic etch processes are difficult to control on a nanoscale, i.e., on a scale from 0.1 nm to 10 nm, because the etch rate is sensitive to temperature and / or supply of etchant.
Advanced semiconductor chips require a high degree of profile control, where the extent of vertical etching may be difficult to control.
This constraint makes it difficult to enable useful features in semiconductor technology such as tunnel field effect transistor (FET) having strained semiconductor-on-insulator (SSOI) features, which may be a crucial component in obtaining sub-threshold slope characteristics below the classical limit of 60 mV / decade.
Method used
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[0025]As stated above, the present invention relates to methods of laterally offsetting sidewalls of a trench in a semiconductor substrate relative to sidewalls of overlying structures and structures formed by the same, which are now described in detail with accompanying figures. The drawings are not necessarily drawn to scale.
[0026]Referring to FIG. 1, a first exemplary structure according to a first embodiment of the present invention includes a substrate 8, a first gate structure 20A located on a top surface of the substrate 8, and a second gate structure 20B located on the top surface of the substrate 8 and laterally spaced from the first gate structure 20A. The substrate 8 includes a semiconductor material layer 10, which is comprised of a semiconductor material. The semiconductor material of the semiconductor material layer 10 can be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium ...
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A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
Description
CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a continuation of U.S. patent application Ser. No. 12 / 561,704, filed on Sep. 17, 2009 the entire content and disclosure of which is incorporated herein by reference.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT[0002]This invention was made with United States government support under Contract No. FA8650-08-C-7806 awarded by Defense Advanced Research Projects Agency (DARPA). The United States government has certain rights in this invention.BACKGROUND[0003]This invention relates to methods of laterally offsetting sidewalls of a trench in a semiconductor substrate relative to sidewalls of overlying structures and structures formed by the same.[0004]Etching in a vertical direction is an integral component of semiconductor processing technology. An isotropic etch employs wet chemicals or reactant gases that etch a material isotropically. The etch rate of isotropic etch processes are difficult to control on a...
Claims
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IPC IPC(8): H01L29/78H01L21/306H01L21/336
CPCH01L21/0237H01L21/02639H01L21/3065H01L29/7848H01L29/165H01L29/66636H01L29/78H01L21/3083Y10S438/938
InventorENGELMANN, SEBASTIAN ULRICHFULLER, NICHOLAS C.M.JOSEPH, ERIC ANDREWLAUER, ISAACMARTIN, RYAN M.VICHICONTI, JAMESZHANG, YING
OwnerGLOBALFOUNDRIES INC