Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor structure with galvanically-isolated signal and power paths

a technology of electromagnetic isolation and signal, applied in the direction of transformer/inductance details, transformer/inductance coil/winding/connection, inductance, etc., can solve the problems of low efficiency, bulky and expensive galvanic isolation with a single power supply, and poor approach to power transfer

Active Publication Date: 2013-02-28
NAT SEMICON CORP
View PDF0 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention relates to a semiconductor structure with galvanically-isolated signal and power paths, and a method for making it. The technical effect of the invention is to provide a more compact and cost-effective way to achieve galvanic isolation in semiconductor structures, which can be used to transfer power without the need for a separate power supply.

Problems solved by technology

However, galvanic isolation with a single power supply tends to be bulky and expensive.
However, the very low efficiency makes this a poor approach to transferring power.)
Although multi-die chip 100 provides galvanic isolation for both the signal and power paths, toroidal transformer 124 tends to be bulky and expensive to manufacture.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure with galvanically-isolated signal and power paths
  • Semiconductor structure with galvanically-isolated signal and power paths
  • Semiconductor structure with galvanically-isolated signal and power paths

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0066]As shown in FIGS. 4A-4D, in a first embodiment, the metal lower structures 316 can be formed by depositing a seed layer 320 to touch the non-conductive top surface 310T of substrate structure 310. For example, seed layer 320 can be implemented with a layer of aluminum copper. Seed layer 320 can alternately be formed by depositing 300 Å of titanium, 3000 Å of copper, and 300 Å of titanium. After seed layer 320 has been formed, a plating mold 322 is formed on the top surface of seed layer 320.

[0067]As shown in FIGS. 5A-5D, following the formation of plating mold 322, copper is electroplated in a conventional manner to form the metal lower structures 316 approximately 5 μm thick. After the electroplating, plating mold 322 and the underlying regions of seed layer 320 are removed to expose the lower plate structures 316S, the lower dummy structures 316D, and the lower coil structures 316C.

second embodiment

[0068]Alternately, in a second embodiment, as shown in FIGS. 6A-6D, the metal lower structures 316 can be formed by sputter depositing a metal layer 324, such as aluminum, onto the non-conductive top surface 310T of substrate structure 310 to a depth of approximately 5 μm. Alternately, metal layer 324 can include multiple layers of metal such as, for example, a layer of titanium, a layer of titanium nitride, a layer of aluminum copper, a layer of titanium, and a layer of titanium nitride.

[0069]Once metal layer 324 has been formed, a patterned photoresist layer 326 approximately 1.0 μm thick is formed on the top surface of metal layer 324 in a conventional manner. Following the formation of patterned photoresist layer 326, metal layer 324 is etched to remove the exposed regions of metal layer 324 and form the metal lower structures 316.

[0070]Metal layer 324 can be etched using a dry etch such as reactive ion etching, or a timed wet etch. For example, aluminum can be wet etched in a 1...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
ground voltageaaaaaaaaaa
ground voltageaaaaaaaaaa
diameteraaaaaaaaaa
Login to View More

Abstract

A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to semiconductor structures and, more particularly, to a semiconductor structure with galvanically-isolated signal and power paths.[0003]2. Description of the Related Art[0004]Galvanic isolation refers to an isolation that prevents a first system from communicating with a second system by way of a flow of electrons from one system to the other system, but which allows the two systems to communicate in other ways. For example, the first system can transmit a signal to the second system using changes in inductance or capacitance, or by using optical or other means.[0005]The first system and the second system commonly have separate power supplies, but a single power supply can also be used where the first system transfers galvanically-isolated power to the second system. A single power supply has the advantage of eliminating the power supply requirements of the second system. However, galvanic...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01F5/00H01L21/02
CPCH01L23/5223Y10T29/41H01L28/10H01L27/0688H01L27/08H01L2224/48H01L2224/48091H01L2224/73265H01L23/5227H01F2027/2809H01L2924/30107H01L2924/00014H01L2924/00
Inventor GABRYS, ANNFRENCH, WILLIAMHOPPER, PETER J.LEE, DOK WONJOHNSON, PETER
Owner NAT SEMICON CORP