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Integrated circuit and method for fabricating the same

a technology of integrated circuits and components, applied in the direction of transistors, basic electric elements, electric devices, etc., can solve the problems of leakage current and thin gate insulation layer of silicon oxide, and achieve the effect of reducing process cost and consuming time, and simple process

Inactive Publication Date: 2013-09-12
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention offers an integrated circuit that combines a high-k / metal gate semiconductor device with a poly-silicon semiconductor device. The process of fabricating this circuit is simple, which reduces the cost and time required for production. Hence, the technical effect of this invention is the decreased process cost and consuming time.

Problems solved by technology

However, a leakage current occurs when the gate insulation layer of silicon oxide becomes thinner.

Method used

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  • Integrated circuit and method for fabricating the same
  • Integrated circuit and method for fabricating the same
  • Integrated circuit and method for fabricating the same

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Embodiment Construction

[0033]Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, it is to be noted that the present invention is not limited thereto. Furthermore, the step serial numbers concerning the saturation adjustment method are not meant thereto limit the operating sequence, and any rearrangement of the operating sequence for achieving same functionality is still within the spirit and scope of the invention. The like numbered numerals designate similar or the same parts, regions or elements. It is to be understood that the drawings are not drawn to scale and are served only for illustration purposes.

[0034]FIGS. 1A-1K illustrate cross-section views of an integrated circuit during the fabricating process thereof according to an embodiment of the present invention. Referring to FIGS. 1A-1E, a substrate 102, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, with a...

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Abstract

An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.

Description

BACKGROUND[0001]1. Technical Field[0002]The present invention relates to an integrated circuit and method for fabricating the same, more particularly to an integrated circuit integrating the high-k / metal gate semiconductor device with the poly-silicon semiconductor device and method for fabricating the same.[0003]2. Description of the Related Art[0004]As the dimension of a semiconductor device is getting less, the dimension of the gate structure and the thickness of the gate insulation layer are reduced accordingly. However, a leakage current occurs when the gate insulation layer of silicon oxide becomes thinner. To reduce the leakage current, a high dielectric constant (high-k) material is used to replace silicon oxide for forming the gate insulation layer. The gate of polysilicon may react with the high-k material to generate a Fermi-level pinning, so that the threshold voltage is increased and the performance of the device is affected. Therefore, a metal layer is used as a gate, ...

Claims

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Application Information

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IPC IPC(8): H01L27/088H01L21/336
CPCH01L21/823807H01L21/823835H01L21/82345H01L21/823857H01L21/823842
Inventor LEE, HSIANG-CHENSHIH, PING-CHIACHEN, KE-CHIWANG, CHIH-MINGHUANG, CHI-CHENG
Owner UNITED MICROELECTRONICS CORP