Method of fabricating semiconductor device and the semiconductor device

a semiconductor device and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve problems such as the difference in the shape of processed films

Inactive Publication Date: 2014-02-13
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances the uniformity of wiring patterns, reduces resistance variations, and improves the buriability of conductive films, thereby enhancing the reliability and efficiency of semiconductor device fabrication.

Problems solved by technology

This results in a problem of a difference in the shape of the processed film.

Method used

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  • Method of fabricating semiconductor device and the semiconductor device
  • Method of fabricating semiconductor device and the semiconductor device
  • Method of fabricating semiconductor device and the semiconductor device

Examples

Experimental program
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Embodiment Construction

[0014]One embodiment will be described with reference to FIGS. 1 to 11. The embodiment is directed to a NAND flash memory. Identical or similar parts are labeled by the same reference symbols throughout the figures, which are schematic and differ in the actual relationship between a thickness and a planar dimension, a ratio among thicknesses of layers and the like.

[0015]Firstly, the configuration of the NAND flash memory will be described. FIG. 1 is an equivalent circuit diagram showing a part of memory cell array formed in a memory cell region of the NAND flash memory. The memory cell array is composed of NAND cell units (memory units) Su arranged in a matrix. Each NAND cell unit includes two selective gate transistors Trs1 and Trs2 and a plurality of memory cell transistors Trm (2n where n is a positive number, 8, for example) series-connected between the selective gate transistors Trs1 and Trs2. In the NAND cell units Su, the memory cell transistors Trm adjacent to each other are...

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Abstract

A method of fabricating a semiconductor device includes forming a plurality of mask patterns by anisotropically etching a mask-forming film until upper surfaces of core patterns are exposed. A facing pair includes a pair of the mask patterns facing the core pattern located between the paired mask patterns. The mask patterns of the facing pair have respective lower portions spaced from each other by a first distance. An adjacent pair includes a pair of mask patterns adjacent to each other with a space having no core pattern. The mask patterns of the adjacent pair have respective lower portions spaced from each other by a second distance. The mask patterns are formed so that the second distance is larger than the first distance.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2009-82060, filed on Mar. 30, 2009, the entire contents of which are incorporated herein by reference.BACKGROUND[0002]1. Field[0003]The present invention relates to a method of fabricating a semiconductor device provided with a microscopic wiring pattern and the semiconductor device.[0004]2. Related Art[0005]A photolithography technique as one of semiconductor processing techniques includes a sidewall transfer process which provides a microscopic wiring pattern exceeding a limit of minimum patterning width of a resist film. For example, Japanese patent application publication, JP-A-2007-43156 discloses the following process through which a semiconductor device is fabricated. Firstly, a resist is patterned by an ordinary lithography technique, and a first film is etched so that core-forming patterns are formed at a predetermined p...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L23/49
CPCH01L23/49H01L21/0337H01L21/31144H01L21/76804H01L21/76816H01L2924/00014H10B41/35H01L2224/05599H01L2224/45099H01L24/42
InventorMATSUNO, KOICHIHIMENO, YOSHIAKI
OwnerKK TOSHIBA