Transceiver including a high latency communication channel and a low latency communication channel

a transceiver and communication channel technology, applied in the field of communication systems, can solve the problems of high latency and the problem of ever-increasing problem of high latency, and achieve the effect of reducing latency in a serdes transceiver

Active Publication Date: 2014-05-08
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]Methods, systems, and apparatuses are described for reducing latency in a SERDES transceiver, substantially as ...

Problems solved by technology

One disadvantage with multi-gigabit transceivers, however, is that they suffer from high latency due to the fact that the incoming high speed signal has to go through many stages of de-serialization...

Method used

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  • Transceiver including a high latency communication channel and a low latency communication channel
  • Transceiver including a high latency communication channel and a low latency communication channel
  • Transceiver including a high latency communication channel and a low latency communication channel

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Embodiment Construction

Introduction

[0018]The present specification discloses numerous example embodiments. The scope of the present patent application is not limited to the disclosed embodiments, but also encompasses combinations of the disclosed embodiments, as well as modifications to the disclosed embodiments.

[0019]References in the specification to “one embodiment,”“an embodiment,”“an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0020]...

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PUM

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Abstract

Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Description

BACKGROUND[0001]1. Technical Field[0002]The present invention relates to communication systems, and in particular, to reducing latency in transceivers.[0003]2. Background Art[0004]Communication systems for transmitting data may operate according to a number of standards and implementations. Such communication systems may include one or more communication channels for transmitting and receiving data. Some of such communication channels may include a transceiver that receives serial data, converts the serial data to parallel data, digitally processes the parallel data, serializes the processed data, and transmits the serialized data. Such a transceiver may be referred to as a SERDES (serializer / deserializer) transceiver. SERDES transceivers may be used in a wide range of communication systems and devices, such as mobile devices, desktop computers and servers, computer networks, and telecommunication networks.[0005]A SERDES transceiver may be capable of handling very high data rates. F...

Claims

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Application Information

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IPC IPC(8): H03D3/02
CPCH03D3/02H03D3/006H04B1/745H04L7/033
Inventor ZHANG, HENGKHANPOUR, MEHDICAO, JUNLIU, CHANGMOMTAZ, AFSHIN
Owner AVAGO TECH INT SALES PTE LTD
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