Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices

Abstract

One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a <100> crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting device structures.[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a g...

AI Technical Summary

Benefits of technology

The present disclosure is directed to methods and device structures for forming low defect replacement fins for a FinFET semiconductor device. The technical effects include reducing the defects in the device, improving the quality and reliability of the device, and optimizing the performance and functionality of the device. These methods involve forming a substrate fin in a substrate, positioning a replacement fin structure above the substrate fin, and forming a gate structure around at least a portion of the replacement fin structure. The orientation of the substrate fin and the position of the replacement fin structure and gate structure can be adjusted to optimize the performance of the device.

Problems solved by technology

However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region.

In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain.

Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability.

However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such materials and silicon.

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