Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits

Inactive Publication Date: 2014-09-18
INTEL CORP
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  • Application Information

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Benefits of technology

[0011]Accordingly, a need exists for a method and apparatus for a more efficient and flexible OOO processor architecture that is configured to reduce the latencies in the multi-cycle “load-to-use” path. Embodiments of the present invention allow a realignment of the timing critical

Problems solved by technology

As a result of the above-listed various stages, the load-to-use path is highly t

Method used

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  • Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
  • Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
  • Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits

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[0027]Reference will now be made in detail to the various embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

NOTATIO...

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Abstract

A microprocessor implemented method for processing a load instruction is disclosed. The method comprises computing a virtual address corresponding to the load instruction. Next, it comprises performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel using early calculated lower address bits of the virtual address. Subsequently, it comprises retrieving a set of entries from the TLB corresponding to a first group of lower address bits transmitted to the TLB, wherein the set of entries comprise a plurality of virtual addresses and corresponding physical addresses. Further, it comprises finding a matching entry for the virtual address in the set of entries using upper bits of the virtual address, wherein the matching entry comprises a physical address corresponding to the virtual address. Finally, it comprises finding a matching entry in the data cache memory using the physical address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a conversion of and claims priority to and the benefit of Provisional Patent Application No. 61 / 799,116, entitled “Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits,” having a filing Date of Mar. 15, 2013, which is herein incorporated by reference in its entirety.FIELD OF THE INVENTION[0002]Embodiments according to the present invention generally relate to microprocessor architecture and more particularly to the architecture for out-of-order microprocessors.BACKGROUND OF THE INVENTION[0003]One of the most critical paths in high-performance processors is the load-to-use path, which is defined as the time between computing the address of a load to writing the data back to registers. An increase in the number of cycles in the load-to-use path directly affects the performance (measured in “instructions per cycle”) of the processor.[0004]The critical components of the...

Claims

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Application Information

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IPC IPC(8): G06F12/10
CPCG06F12/1054G06F9/30043
Inventor ABDALLAH, MOHAMMAD A.RAO, RAVISHANKAR
Owner INTEL CORP
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