Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits

Abstract

A microprocessor implemented method for processing a load instruction is disclosed. The method comprises computing a virtual address corresponding to the load instruction. Next, it comprises performing a lookup of a set associative translation lookaside buffer (TLB) and a set associative data cache memory in parallel using early calculated lower address bits of the virtual address. Subsequently, it comprises retrieving a set of entries from the TLB corresponding to a first group of lower address bits transmitted to the TLB, wherein the set of entries comprise a plurality of virtual addresses and corresponding physical addresses. Further, it comprises finding a matching entry for the virtual address in the set of entries using upper bits of the virtual address, wherein the matching entry comprises a physical address corresponding to the virtual address. Finally, it comprises finding a matching entry in the data cache memory using the physical address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a conversion of and claims priority to and the benefit of Provisional Patent Application No. 61 / 799,116, entitled “Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits,” having a filing Date of Mar. 15, 2013, which is herein incorporated by reference in its entirety.FIELD OF THE INVENTION[0002]Embodiments according to the present invention generally relate to microprocessor architecture and more particularly to the architecture for out-of-order microprocessors.BACKGROUND OF THE INVENTION[0003]One of the most critical paths in high-performance processors is the load-to-use path, which is defined as the time between computing the address of a load to writing the data back to registers. An increase in the number of cycles in the load-to-use path directly affects the performance (measured in “instructions per cycle”) of the processor.[0004]The critical components of the...

AI Technical Summary

Benefits of technology

The present invention provides a method and apparatus for a more efficient and flexible OOO processor architecture that reduces latencies in the multi-cycle "load-to-use" path. It allows for a faster and more efficient path with no loss of performance by realignment of the timing critical load-to-use path. It also advantageously allows for higher frequencies since the load-to-use critical path is often the limiting part of the microprocessor architecture. By using the early calculated lower order bits of a virtual address of a load instruction, the access time to the memory structures in the processor pipeline is reduced and the latencies in the load-to-use path are advantageously reduced. The invention also uses the early calculated lower order bits of the virtual address to create a unique hash and perform a partial match in a Load Store Queue, which simplifies any subsequent compare operation.

Problems solved by technology

As a result of the above-listed various stages, the load-to-use path is highly time intensive in conventional processors and can result in undesirable latencies.

Images