Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor device

a semiconductor and chip technology, applied in the field of semiconductor device layout, can solve the problems of increasing the resistance of the contact hole, increasing the chip area, and severe design restrictions on the arrangement of the signal wiring in the conventional standard cell structure, and achieve the effect of not increasing the area

Active Publication Date: 2015-01-15
SOCIONEXT INC
View PDF4 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent aims to ensure that the wiring resources and power supply are provided to the substrate without adding to the area.

Problems solved by technology

Thus, the conventional standard cell structure has severe design restrictions on arrangement of the signal wiring.
As a result, the problem is that a chip area is increased.
According to the above conventional tap cell, the problem is that in a case where the contact hole is defectively formed, resistance of the contact hole is increased or an open failure is generated.
In order to avoid the above problems, the number of the contact holes is to be increased, but when the number of the contact holes is increased, the problem is that an area of the semiconductor device is increased.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

first exemplary embodiment

Variation of First Exemplary Embodiment

[0042]Next, a variation of the first exemplary embodiment will be described with reference to FIG. 2. FIG. 2 is a plan view showing a layout structure of a semiconductor device according to the variation of the first exemplary embodiment. In addition, as for a component similar to that in the first exemplary embodiment described with reference to FIGS. 1A to 1C, the component is marked with the same reference and its description is omitted.

[0043]This variation differs from the first exemplary embodiment described with reference to FIGS. 1A to 1C in that there is no contact hole 2 for connecting local wiring 3b to potential supply wiring 1, and no contact hole 2b for connecting local wiring 3b to potential supply wiring 1b.

[0044]According to this variation, potential supply wirings 1 and 1a supply the potential to local wiring 3a, but potential supply wirings 1 and 1b do not supply the potential to local wiring 3b.

[0045]This variation of the f...

second exemplary embodiment

[0046]Next, the second exemplary embodiment will be described with reference to the drawings. FIGS. 3A to 3C are views each showing a structure of a semiconductor device according to the second exemplary embodiment. FIG. 3A is a plan view showing a layout structure, FIG. 3B is a cross-sectional view taken along a line X-X in FIG. 3A, and FIG. 3C is a cross-sectional view taken along a line Y-Y in FIG. 3A. In addition, as for a component similar to that in the first exemplary embodiment described with reference to FIG. 1, the component is marked with the same reference and its description is omitted.

[0047]This exemplary embodiment differs from the first exemplary embodiment described with reference to FIG. 1 in that wiring widths of local wirings 3c and 3d are larger than the wiring widths of local wirings 3a and 3b, respectively. In addition, as shown in FIG. 3C, local wirings 3c and 3d overlap with dummy gates 6a and 6b, respectively. Dummy gate 6 has no function in a circuit opera...

third exemplary embodiment

[0050]Next, the third exemplary embodiment will be described with reference to the drawings. FIGS. 4A to 4C are views each showing a structure of a semiconductor device according to the third exemplary embodiment. FIG. 4A is a plan view showing a layout structure, FIG. 4B is a cross-sectional view taken along a line X-X in FIG. 4A, and FIG. 4C is a cross-sectional view taken along a line Y-Y in FIG. 4A. In addition, as for a component similar to that in the first exemplary embodiment described with reference to FIGS. 1A to 1C, the component is marked with the same reference and its description is omitted.

[0051]This exemplary embodiment differs from the first exemplary embodiment described with reference to FIGS. 1A to 1C in that while the wiring widths of local wirings 3a and 3c are partially enlarged in the first exemplary embodiment, local wirings 3e and 3f both have a constant wiring width of W1 in the third exemplary embodiment shown in FIGS. 4A to 4C. In addition, this exemplar...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
conductivityaaaaaaaaaa
widthsaaaaaaaaaa
speedaaaaaaaaaa
Login to View More

Abstract

A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.

Description

[0001]This is a continuation of International Application No. PCT / JP2013 / 002675, with an international filing date of Apr. 22, 2013, which claims priority of Japanese Patent Application No. 2012-098434, filed on Apr. 24, 2012, the contents of each of which are hereby incorporated by reference.BACKGROUND[0002]1. Technical Field[0003]The present disclosure relates to a layout of a semiconductor device, and more particularly to a semiconductor device capable of achieving increased speed and increased degree of integration.[0004]2. Description of the Related Art[0005]According to a conventional semiconductor device, a transistor is formed in each of an N-type well region and a P-type well region that are formed so as to extend in a horizontal direction, and the N-type well regions and the P-type well regions are alternately arranged in a vertical direction. The above structure is known as a standard cell structure in general.[0006]According to the conventional standard cell structure (s...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/092H01L23/538H01L29/423H01L27/02
CPCH01L29/4232H01L27/0928H01L27/0207H01L23/5386H01L21/823871H01L2924/0002H01L2924/00
Inventor SHIMBO, HIROYUKITAMARU, MASAKI
Owner SOCIONEXT INC