Gen3 pci-express riser

Abstract

A Gen3 PCIe Riser consisting of four PCIe x16 slots, a PCIe switch, external power, a remote programming interface, and a PCIe edge connector. The PCIe switch is programmed to allow any PCIe device installed in a PCIe slot to communicate directly through the switch with another PCIe device installed in another PCIe slot on the Riser without using the processing power of a Central Processing Unit thereby increasing system efficiency. In alternative embodiments, two Gen3 PCIe Risers are cross-connected to allow for more direct communication between any PCIe devices installed in the system. External power is connected when the PCIe devices require more power than available from a standard PCIe slot. The external programming interface allows for the configuration of the PCIe switch to be modified to meet system demands.

Description

RELATED APPLICATIONS[0001]This application is a conversion of, and claims the benefit of priority to, U.S. Provisional Patent Application Ser. No. 61 / 986,813, entitled “Gen3 PCI-Express Riser”, filed Apr. 30, 2014, and currently co-pending.FIELD OF THE INVENTION[0002]The present invention relates generally to computer systems. The present invention is more particularly useful as device to reduce processing demands on a Central Processing Unit (CPU) in a computer system by allowing devices connected to the present invention to communicate with each other without using the CPU thereby allowing it to perform other tasks while the connected devices communicate with each other.BACKGROUND OF THE INVENTION[0003]The expansion card in the computing environment is typically a printed circuit board that can be inserted into an expansion slot. Expansion slots are connected to the computer system by an expansion bus, which moves information between the internal hardware of a computer system, inc...

AI Technical Summary

Benefits of technology

The present invention introduces a new Gen3 PCIe Riser that includes four PCIe x16 Slots and an edge connector. This design allows the Riser to be easily inserted into a PCIe slot on a computer motherboard. The dedicated bus interface with a PCIe switch avoids data corruption caused by multiple devices accessing the bus simultaneously. Additionally, the PCIe switch allows for seamless communication between various PCIe devices installed on different Gen3 PCIe Risers, regardless of whether they are connected to the same CPU or not. This results in faster data transfer and reduced latency in the computer system.

Problems solved by technology

This bus was difficult to work with since a person needed in-depth knowledge of the motherboard and the expansion card to configure jumpers and switches to match the settings in the expansion card's driver since the ISA bus was so closely linked to the speed of the processor, which varied from computer to computer.

Also, the input / output (I / O) bandwidth of the ISA bus was limited due to the clock speed limitations of the physical design of the connectors.

As time progressed, it became apparent that the architecture of the ISA bus had become a limiting factor in a computer's performance and a new architecture was needed.

In the early 1990s, the I / O bandwidth of the ISA bus was becoming a critical bottleneck for graphics.

When Intel introduced the Pentium© processor, there were major differences in its bus designs and was not easily adaptable to the VLB design.

This became a problem if the computer system required multiple expansion cards with increased performance.

The VLB also had reliability problems due to strict electrical limitations.

These limitations led to electrical glitches involving the CPU, memory, and other expansion cards.

The VLB also had limited scalability due to it being tightly coupled to the bus speeds of the processor itself.

As processor speeds increased, the design limitations of the VLB did not allow it to maintain signal integrity when moving data at the higher rate.

Lastly, VLB cards were notoriously large for the functions they performed.

Due to the increased size, excessive force was needed to install or remove the card, usually over-stressing the motherboard and the card itself leading to premature failure of the motherboard, the card, or both.

However, the cost of implementing PCI-X was high due to the need to create a 64-bit bus on the motherboard, which takes up valuable space.

Poor materials and crossover signal from nearby wires translate into noise, which slows the connection down.

The additional width of a PCI-X bus means it can carry more data, which can generate even more noise.

The PCI protocol also does not prioritize data, so more important data can get caught in the bottleneck when lower priority data is serviced by the system.

The main limitation of expansion slots in computers is the number of available slots for the given size of motherboard.

If the function of a computer system depends on the installed expansion cards, there may not be sufficient slots available to incorporate all of the necessary functions into the system.

Latency is usually attributed to propagation issues, the transmission medium, routers, storage delays, and other computer processes.

Specific contributors to computer latency include mismatches in data speed between the CPU and I / O devices as well as inadequate data buffers.

If the amount of data to be transferred is large or continuous, the latency associated with the transfer can result in a significant amount of delay and a reduction in system performance.

Using a peripheral bus occupies the CPU during the read / write process and does not allow other work to be performed until the operation is completed.

If the system is dominated by GPUs, additional functions performed by the system may experience delay, or latency, when the GPUs communicate with each other.

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