Overlay marks and semiconductor process using the overlay marks

Abstract

An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes or system integration tests. More specifically, the present invention relates to overlay marks for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer stack and the semiconductor process using the overlay marks.[0003]2. Description of the Prior Art[0004]As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The...

AI Technical Summary

Benefits of technology

[0009]This invention will describe a novel configuration of correspondingly arranging and disposing the overlay/alignment marks based on their underlying patterns. The configur

Problems solved by technology

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET).

Regardless of whether a mask is error-free, if all or part of the mask is not aligned properly, the resulting features may not align correctly with adjoining layers.

This can result in reduced device performance

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