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Semiconductor device, semiconductor chip, and test method for semiconductor chip

a semiconductor chip and semiconductor technology, applied in the field of semiconductor devices, can solve the problems of increasing the size of the semiconductor device, reducing the area that could be taken up by circuitry for primary functions, etc., and achieve the effect of increasing the size of the devi

Active Publication Date: 2017-11-02
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device, chip, and test method for a chip that allows for pre-shipping tests without degrading output or increasing device size. The chip can be tested using existing output pads without the need for additional test pads for contact with a probe needle. The output signal generated in the chip's internal signal processing circuit is sent directly to the output pad without passing through a switch element for testing. This results in improved performance and reliability during pre-shipment testing.

Problems solved by technology

However, there was a problem that in the above-mentioned semiconductor device, test pads having a surface area sufficient for the probe needle to come into contact therewith needed to be further provided for testing, and as a result, the area that could be taken up by circuitry for primary functions was proportionally reduced.
Thus, there was a problem that in order to attain desired through rate characteristics for the output buffer, a transistor with low on resistance would need to be used for the switch element, and such a transistor would have a larger surface area, resulting in an increase in size of the semiconductor device.

Method used

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  • Semiconductor device, semiconductor chip, and test method for semiconductor chip
  • Semiconductor device, semiconductor chip, and test method for semiconductor chip
  • Semiconductor device, semiconductor chip, and test method for semiconductor chip

Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0032]FIG. 1 is a circuit diagram showing an example of a circuit formed in a semiconductor chip 10 after manufacturing. As shown in FIG. 1, the semiconductor chip 10 has formed therein a signal processing circuit MC, output buffers B1 to Bn (n being an integer of 2 or greater), a testing circuit TC, and output pads OT1 to OTn.

[0033]The signal processing circuit MC is configured to supply to the output buffers B1 to Bn data signals D1 to Dn generated by performing a signal process (explanation omitted) required for the semiconductor chip 10.

[0034]The output buffers B1 to Bn are configured to supply, to the testing circuit TC through lines L1 to Ln, output data signals DD1 to DDn generated by individually amplifying the data signals D1 to Dn by a gain of 1, for example. Among the lines L1 to Ln, the lines L2 to Ln are individually connected to the output pads OT2 to OTn of the semiconductor chip 10.

[0035]The testing circuit TC has switch elements SW1 to SWn provided for each of the b...

embodiment 2

[0058]FIG. 5 is a circuit diagram showing a circuit according to Embodiment 2 formed in a semiconductor chip 10 after manufacturing. The configuration shown in FIG. 5 is similar to that of FIG. 1 except that a testing control unit TCUa is used instead of the testing control unit TCU shown in FIG. 1, a switch element SWx is additionally provided as a common output switch, and a switch element SWy is additionally provided as a grounding switch.

[0059]The switch element SWx configured to be set on or off according to a switching signal Sx. When the switch element SWx is set to be on, the output line QL and the common output line TL are connected. On the other hand, when the switch element SWx is set to be off, the output line QL is disconnected from the common output line TL. It is preferable that the switch element SWx be formed in the vicinity of the output line QL.

[0060]The switch element SWy is configured to be set on or off according to a switching signal Sy. In this case, when the...

embodiment 3

[0066]FIG. 7 is a circuit diagram showing a circuit according to Embodiment 3 formed in a semiconductor chip 10 after manufacturing. The configuration shown in FIG. 7 is the same as that of FIG. 1 except that shorting pads P2T to PnT for connecting the shorting wiring line are each formed in the lines L2 to Ln. In this case, it is preferable that the shorting pads P2T to PnT be disposed in a position such that the length of the line L(t) from the output terminal of the output buffer B(t) (t being an integer of 2 to n) to the shorting pad P(t)T is equal to the length of the line L1 from the output terminal of the output buffer B1 to the shorting pad P1T.

[0067]Even when the configuration shown in FIG. 7 is adopted for the testing circuit TC, testing of the semiconductor chip 10 is performed according to the system configuration shown in FIG. 2 in a manner similar to the configuration shown in FIG. 1. In this case, the test operation for when the configuration shown in FIG. 7 is adopte...

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PUM

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Abstract

A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

Description

BACKGROUND OF THE INVENTIONBackground Arts[0001]The present invention relates to a semiconductor device, and in particular, a semiconductor device including a test circuit, a semiconductor chip, and a test method for a semiconductor chip.Background Arts[0002]Prior to shipping, semiconductor devices are tested in order to confirm whether or not a desired output signal is outputted from an output terminal when a prescribed signal is applied to an input terminal. When performing the test, a probe needle is placed in contact with a pad that is connected to each output terminal of the semiconductor device, and the output signal is acquired through the probe needle, for example.[0003]In the case of semiconductor devices with a large number of output terminals such as driver ICs for display panels, in order to mitigate an increase in IC chip area resulting from the increase in the number of output terminals, it is desirable for the space between adjacent pads to be narrowed.[0004]In such a...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/66G01R31/26H01L23/522H01L23/525H01L23/00
CPCH01L22/32H01L24/48H01L23/525H01L2224/48132H01L22/14G01R31/2644H01L23/5228H01L22/34H01L2924/181G01R31/2856G01R31/2884H01L2924/00012
Inventor MASAI, HIDEKI
Owner LAPIS SEMICON CO LTD