Memory device, memory system including the same, and operation method thereof

Abstract

A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2016-0179338, filed on Dec. 26, 2016, which is incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]Exemplary embodiments relate to a memory system, and more particularly, to a memory system for performing a refresh operation of a memory device and an operation method thereof.2. Description of the Related Art[0003]A volatile memory device such as a Dynamic Random Access Memory (DRAM) may configure a memory cell for storing data by using a transistor serving as a switch and a capacitor for storing data in the form of a charge. Accordingly, a logic high level or a logic low level of data may be determined according to the charge in the capacitor of the memory cell, that is, whether a voltage across the capacitor is high or low.[0004]In principle, there should be no power consumption involved in the storing of data, since the storing of data invol...

AI Technical Summary

Benefits of technology

The present invention provides an operation method for a memory system that can efficiently compare and match input addresses with target addresses. This method includes increasing a count for addresses that match the input address when the input address does not match with the target addresses. The input address is then updated based on the counts when the input address does not match with the recently inputted addresses. This helps to improve the efficiency and accuracy of the memory system.

Problems solved by technology

However, it is well known that the initial amount of charge stored in the capacitor of a memory cell may decrease over time due to a leakage current caused by a PN junction of a MOS type transistor employed in the memory cell and eventually the stored charge i.e., the stored data may be lost.

Meanwhile, because of the continuous increase in the degree of integration of memory devices, the interval between adjacent word lines in the memory device is reduced, which may result in an increase of a coupling effect between adjacent word lines.

Because of the coupling effect, when a certain word line is frequently activated, the data of memory cells electrically coupled to adjacent word lines may be damaged.

Furthermore, since an electromagnetic wave generated when the word line is toggled between the activated state and the precharged state enables inflow / outflow of electrons of the cell capacitors included in the memory cells electrically coupled to adjacent word lines, data of the memory cells may be damaged.

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