Method of manufacturing chip package structure with conductive pillar

Abstract

A method of manufacturing a chip package structure comprising: disposing a first semiconductor component on a first carrier, wherein the first semiconductor component comprising a first active surface and a plurality of first pads disposed on the first active surface; forming a plurality of first conductive pillars on the first pads, wherein each of the first conductive pillars is a solid cylinder comprising a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface; forming a first encapsulant to encapsulate the first semiconductor component and the first conductive pillars, wherein the first encapsulant exposes the top surface of each of the first conductive pillars; forming a first redistribution layer on the first encapsulant, wherein the first redistribution layer is electrically connected to the first conductive pillars; and removing the first carrier.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is a divisional application of U.S. application Ser. No. 15 / 599,477, filed on May 19, 2017, now allowed, which claims the priority benefit of U.S. provisional application Ser. No. 62 / 385,257, filed on Sep. 9, 2016. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification.BACKGROUND OF THE INVENTIONField of the Invention[0002]The present invention generally relates to chip package structure and a manufacturing method thereof. More particularly, the present invention relates to a stacked type chip package structure and a manufacturing method thereof.Description of Related Art[0003]Recently, attention has paid to a semiconductor device called a “substrate with a built-in chip” in which a chip and the like are buried in a substrate made of resin and the like and a semiconductor device in which an insulating layer and a wiring layer are formed on...

AI Technical Summary

Benefits of technology

The present invention is a chip package structure and manufacturing method that improves reliability and yield while reducing production cost and overall thickness. The chip package structure includes a semiconductor component with conductive pillars formed on it, which are then encapsulated and connected by a redistribution layer. Multiple semiconductor components can be stacked on top of each other, and the process can be repeated to create a stacked structure. This reduces the thickness of the chip package and avoids damage to the pads of the semiconductor component, resulting in better electrical performance and a smaller gap between conductive pillars. The method also eliminates the need for expensive and time-consuming laser drilling processes.

Problems solved by technology

As a result, the device including a semiconductor chip is disadvantageously damaged.

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