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Semiconductor package having a semiconductor die on a plated conductive layer

Active Publication Date: 2020-06-18
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present disclosure provides semiconductor packages, devices, and methods in which a semiconductor die is positioned on a plated conductive layer and is recessed with respect to a lower, exterior surface of an encapsulation material. This allows for more efficient use of space and better protection of the semiconductor die. The technical effects include improved performance, reliability, and reduced size of semiconductor packages.

Problems solved by technology

Conventional QFN packages are generally limited in terms of thickness, with the thickness of such packages being limited at least in part by the thickness of the lead frame.

Method used

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  • Semiconductor package having a semiconductor die on a plated conductive layer
  • Semiconductor package having a semiconductor die on a plated conductive layer
  • Semiconductor package having a semiconductor die on a plated conductive layer

Examples

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Embodiment Construction

[0013]In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with semiconductor dies, lead frames, and semiconductor packaging have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the various embodiments provided herein.

[0014]Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.” Further, the terms “first,”“second,” and similar indicators of sequence are to be construed as being interchangeable unless the con...

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PUM

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Abstract

In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.

Description

BACKGROUNDTechnical Field[0001]Embodiments of the present disclosure are generally directed to semiconductor packages having a die pad and leads, and methods of forming semiconductor packages.Description of the Related Art[0002]Semiconductor packages generally include one or more semiconductor electronic components, such as a semiconductor die including one or more integrated circuits (ICs), and a casing to protect the semiconductor die and other internal electronic components. Semiconductor packages come in many forms, including ball grid array (BGA) packages, land grid array (LGA) packages, and quad flat no-lead (“QFN”) packages.[0003]QFN packages typically include a lead frame having a back surface of a die pad exposed on a back side of the package. Leads are also exposed on the back side of the package and are spaced apart from and surrounding the die pad. Within the package, the lead frame supports a die in a central position and often includes wire bonds from the die to the le...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/31H01L23/00H01L21/48H01L21/56
CPCH01L24/48H01L23/49582H01L24/85H01L23/49503H01L21/4821H01L21/568H01L2224/48177H01L23/49541H01L23/3107H01L23/4952H01L23/49548H01L23/3121H01L2224/85H01L21/4832H01L2224/48471H01L2224/32257H01L2224/48248H01L24/32H01L2924/18301H01L2224/48091H01L2924/181H01L2224/73265H01L2924/00014H01L24/73H01L2224/85001H01L2224/83001H01L24/83H01L2924/00012H01L2224/45099
Inventor TALLEDO, JEFFERSON
Owner STMICROELECTRONICS SRL