INTEGRATED CIRCUITS (ICs) EMPLOYING FRONT SIDE (FS) BACK END-OF-LINE (BEOL) (FS-BEOL) INPUT/OUTPUT (I/O) ROUTING AND BACK SIDE (BS) BEOL (BS-BEOL) POWER ROUTING FOR CURRENT FLOW ORGANIZATION, AND RELATED METHODS

Abstract

Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input / output (I / O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I / O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

Description

BACKGROUND1. Field of the Disclosure[0001]The field of the disclosure relates to integrated circuits (ICs) and related IC packages that include one or more semiconductor dice attached to a package structure to provide an electrical interface to the semiconductor dice.II. BACKGROUND[0002]Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in an IC package, also called a “semiconductor package” or “chip package.” The IC package includes one or more semiconductor dice as an IC(s) that are mounted on and electrically coupled to a package substrate to provide physical support and an electrical interface to the semiconductor die(s). The package substrate may be an embedded trace substrate (ETS), for example, that includes embedded electrical traces in one or more dielectric layers and vertical interconnect accesses (vias) coupling the electrical traces together to provide electrical interfaces between the semiconductor die(s). The semiconductor die(s) is ...

AI Technical Summary

Benefits of technology

This patent is about a method to reduce complexity and resistance in a semiconductor device. The method involves using two layers of metallization, called FS-BEOL and BS-BEOL, on the front and back sides of the semiconductor layer. The FS-BEOL layer is used for routing input / output (I / O) signals and power signals, while the BS-BEOL layer is used for power signal routing. By using this method, the number of connections between the semiconductor device and the external package can be reduced, which reduces I / O signal resistance and simplifies the process of routing the signals.

Problems solved by technology

However, to avoid the need to re-route the power signals through power routing lines to semiconductor devices through the FS-BEOL metallization structure, which may increase routing density and complexity in the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to power routing in the BS-BEOL metallization structure.

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