System and method for correcting connectivity errors in a mask layout file

Abstract

A system and method for correcting connectivity errors in a mask layout are disclosed. The method includes comparing a first connection in a mask layout file to a second connection in a schematic netlist. A connectivity error is identified if the first connection does not match the second connection and the identified connectivity error is automatically corrected in the mask layout file.

Description

RELATED APPLICATIONS[0001]This application is a continuation-in-part of U.S. patent application Ser. No. 09 / 414,155, filed Oct. 8, 1999 now abandoned and entitled “AUTOMATIC FIX (CORRECTION) OF ACTIVITY MISMATCHES (LVS: IC LAYOUT VERSUS IC SCHEMATICS) THROUGHOUT GLOBAL MASK LAYOUT DATABASE (IC LAYOUT) COMPUTER SOFTWARE.”TECHNICAL FIELD OF THE INVENTION[0002]This invention relates in general to the field of integrated circuit design, and more particularly to a method for correcting connectivity errors in a mask layout file.BACKGROUND OF THE INVENTION[0003]Over the past several years, the number of transistors in semiconductor devices has increased dramatically. Due to this increase, the time to design and manufacture semiconductor devices has also increased.[0004]A typical semiconductor design process includes numerous steps. Initially, a schematic diagram that represents an integrated circuit is prepared. The schematic diagram provides a representation of the logical connections bet...

AI Technical Summary

Benefits of technology

[0007]In accordance with the present invention, the disadvantages and problems associated with correcting connectivity errors in a mask layout file have been substantially reduced or eliminated. In a particular embodiment, an automated method for correcting connectivity errors in a mask layout database includes identifying a connectivity error in the mask layout file and automatically correcting the connectivity error in the mask layout file.

[0010]Important technical advantages of certain embodiments of the present invention include a layout versus schematic (LVS) tool that reduces the design time for an integrated circuit. The LVS tool checks a mask layout file for connectivity errors and identifies any errors in an output file. If connectivity errors are identified, the LVS tool automatically removes any mismatched connections and replaces the mismatched connections with electrical connections that match the corresponding logical connections in a schematic diagram. By integrating the ability to check for connectivity Thy errors with the ability to correct the connectivity errors, the time needed for the verification process for the mask layout file is substantially reduced.

[0011]Another important technical advantage of certain embodiments of the present invention includes an LVS tool that adds electrical connections to a mask layout file without introducing design rule errors. The LVS tool locates a path in the mask layout file to add an electrical connection that matches the corresponding logical connection from a schematic diagram. When routing the electrical connection, the LVS tool uses design rules from a technology file for a specific manufacturing process and routes the electrical connection to avoid creating any design rule errors. The need for another design rule error check is therefore eliminated.

Problems solved by technology

This comparison may result in connection mismatches between the schematic diagram and the mask layout database.

This process of adding the new electrical connection may take several hours or days to complete.

Furthermore, the layout designer may introduce design rule errors in the mask layout database when adding the new connection.

Eliminating the design rule errors may additionally require several more hours or days and thus, increase the design time for the integrated circuit.

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