Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle

Abstract

A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION[0001]The present application is a continuation application of co-pending U.S. patent application Ser. No. 09 / 452,274, filed on Nov. 30, 1999, now U.S. Pat. No. 6,647,506 entitled “Universal Synchronization Clock Signal Derived Using Single Forward And Reverse Direction Clock Signals Even When Phase Delay Between Both Signals Is Greater Than One Cycle” and assigned to the present assignee, which relates to the subject matter disclosed in U.S. patent application Ser. No. 09 / 369,636 filed on Aug. 6, 1999, entitled “INPUT / OUTPUT INTERFACING FOR A SEMICONDUCTOR CHIP,” now U.S. Pat. No. 6,477,592, both of which are incorporated in their entirety herein by reference.TECHNICAL FIELD OF THE INVENTION[0002]The present invention relates generally to the field of electronic devices, and more particularly, to a system and method for universal synchronization clock.BACKGROUND OF THE INVENTION[0003]In the field of electronics, a collection of wires or ...

AI Technical Summary

Benefits of technology

"The present invention provides a synchronous bus system with a clock line that can be extended without being matched with the data bus. The system derives a universal synchronization clock signal that can be used as a reference clock by all devices in the system. Skew correction circuitry is provided to compensate for clock-data skew and avoid errors in the system. The system also synchronizes all data I / O transactions to the universal synchronization clock signal, resulting in a high-speed, synchronous bus system."

Problems solved by technology

A significant problem with synchronous bus systems, however, is clock-data skew.

Clock-data skew is caused mainly by a mismatch between a transmission line for the clock signal and the transmission lines of the data I / O buses.

This mismatch may be attributable to differences in length, impedance, or other variables.

In high-speed computer systems, the amount of clock-data skew may exceed the period of a clock cycle, in which case, the transfer of data becomes more complicated and difficult if a synchronous bus system is used.

This is impractical, however, because modern computer systems require clock lines and data buses with relatively long lengths in order to support extensibility.

A disadvantage of this previously developed technique for a bus system is its relative complexity.

Because all clock lines must be perfectly matched, the system cannot be easily implemented in practice.

Another disadvantage of the technique is that the operating frequency of the bus system depends on the propagation delay of the data bus.

A disadvantage of this previously developed technique is the requirement that all signals be perfectly matched.

More specifically, in a printed circuit board (PCB) design, it is very difficult to match all signals due to various uncontrollable factors, such as variation in the length and width of the bus, mismatch of material characteristics, and corner effects of the bus.

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