Liquid crystal display apparatus having pixels with low leakage current
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first embodiment
[0028
[0029]First, an overall configuration of a liquid crystal display apparatus according to an embodiment of the present invention is described.
[0030]Referring to FIG. 1, a liquid crystal display apparatus 5 includes a liquid crystal array portion 20, a gate drive circuit 30, and a source drive circuit 40. Liquid crystal array portion 20 includes a plurality of pixels 10 arranged in rows and columns. Corresponding to each row of pixels (hereinafter also referred to as “a pixel row”), a first gate line GL and a second gate line GL# are arranged. Further, corresponding to each column of pixels (hereinafter also referred to as “a pixel column”), a data line DL is arranged. FIG. 1 representatively shows pixels in the first and second columns in the first row, and corresponding gate lines GL1, GL1# and data lines DL1, DL2.
[0031]Gate drive circuit 30 controls the voltage of gate lines GL, GL# so that gate lines GL, GL# are set to a select state in a scanning period and set to a non-sele...
second embodiment
[0097
[0098]FIG. 7 is an equivalent circuit diagram showing a configuration example of a pixel according to a second embodiment.
[0099]A pixel 11 shown in FIG. 7 can be employed in place of pixel 10 in the overall configuration diagram of FIG. 1.
[0100]Referring to FIG. 7, pixel 11 according to the second embodiment is different from pixel 10 according to the first embodiment shown in FIG. 6 in that storage capacitor 14 is connected between pixel electrode node Np and a common electrode node Nc. Further, common voltage VCOM of common electrode node Nc is supplied as AC voltage with amplitude VD that is set alternately to low voltage VCOML and high voltage VCOMH in a constant cycle, as in pixel 11# in FIG. 3. Specifically, pixel 11 includes N-type TFT element 19 additionally to the components of pixel 11# of the comparative example shown in FIG. 3.
[0101]Similarly to pixel 10 shown in FIG. 4, each gate of N-type TFT elements 16, 18 is connected to gate line GL, while the gate of N-type T...
third embodiment
[0111
[0112]In the first and second embodiments, the configuration of a pixel is described in which a TFT element, of which gate voltage is set to intermediate voltage VGM in a non-select state, is provided in a leakage current path, to achieve both of leakage current suppression and protection of a gate insulation film of TFT element.
[0113]Though such a configuration is desirable for protecting a TFT element in a normal operation, it can not provide a desired stress to a TFT element in an acceleration test for screening defects in which a larger stress than in a normal operation is intentionally applied on the TFT element (a burn-in test). In the burn-in test, since the operation is tested under more severe condition than in a normal operation, i.e., in high temperatures and by applying a large voltage stress for a prescribed period, it is desirable to have a configuration that can provide sufficient voltage stress in a short time in order to perform the test effectively.
[0114]In a ...
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