Memory device including a plurality of capacitors

a memory device and capacitor technology, applied in capacitors, digital storage, instruments, etc., can solve the problems of difficult to form an oxide ferroelectric layer on the surface of the substrate, difficult to utilize the mfs structure in practical application, and many problems

Inactive Publication Date: 2008-09-23
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This configuration enables stable information storage and retrieval with improved data retention and high-speed operation by propagating polarization across the ferroelectric layer, reducing the need for hysteresis characteristics and preventing deterioration, and allows for reduced ferroelectric layer thickness.

Problems solved by technology

However, these 1T FeRAMs have many problems.
In the MFS structure, since the surface of a group-IV semiconductor substrate formed of silicon or germanium is easily oxidized, it is very difficult to form an oxide ferroelectric layer on the surface of the substrate.
This makes it difficult to utilize the MFS structure in practical application.
FeRAMs having the MFIS structure or the MFMIS structure also suffer from the same problem.
However, these FeRAMs have problems such as the fatigue of the ferroelectric film and the electrode and deterioration in data retention characteristics due to deformation in the hysteresis loop.

Method used

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  • Memory device including a plurality of capacitors
  • Memory device including a plurality of capacitors
  • Memory device including a plurality of capacitors

Examples

Experimental program
Comparison scheme
Effect test

experimental examples

2. EXPERIMENTAL EXAMPLES

2.1. First Experimental Example

[0092]FIGS. 9, 10A, and 10B show the results of an example of an experiment on the memory device according to the invention.

[0093]The objective of the experiment is to demonstrate that a polarization reversal in a first capacitor propagates to the adjacent second capacitor.

[0094]As shown in FIG. 9, a sample used for this experiment includes the lower electrode 1 formed of platinum, the ferroelectric layer 2 formed of PZTN (Pb(Zr,Ti,Nb)O3) on the lower electrode 1, the charge compensation layer 7 formed of nickel oxide, and two upper electrodes 3a and 3b formed of platinum on the charge compensation layer 7. This sample is referred to as Sample 1. In Sample 1, a capacitor C1 including the upper electrode (saturated polarization forming electrode) 3a and a capacitor C2 including the upper electrode (reading electrode) 3b are connected in parallel. The upper electrode 3a and 3b are both 250 micrometers in width, and the interval be...

second experimental example

2.2. Second Experimental Example

[0099]FIG. 11 is a view showing a sample used in this experiment example. The sample used for this experiment includes the lower electrode 10 formed of platinum, the ferroelectric layer 2 formed of PZTN (Pb(Zr,Ti,Nb)O3) on the lower electrode 10, the charge compensation layer 14 formed of nickel oxide, and the upper electrodes (saturated polarization forming electrode 22, writing electrode 24, and reading electrode 26) formed of platinum on the charge compensation layer 14. The thickness of the ferroelectric layer 2 was 150 nanometers, and the thickness of the charge compensation layer 14 was 20 nanometers. The upper electrodes 22, 24, and 26 were in the shape of a 100-micrometer square, and the interval between the upper electrodes was 20 micrometers.

[0100]The capacitor including the saturated polarization forming electrode 22 is referred to as a first capacitor C1. The capacitor including the writing electrode 24 is referred to as a second capacitor...

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PUM

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Abstract

A memory device including: a lower electrode; a ferroelectric layer formed above the lower electrode; a charge compensation layer formed above the ferroelectric layer and including an oxide having a composition differing from a composition of the ferroelectric layer; and upper electrodes formed above the charge compensation layer. The upper electrodes includes: a saturated polarization forming electrode used for forming a domain polarized to saturation in a predetermined direction in a predetermined region of the ferroelectric layer; a writing electrode disposed apart from the saturated polarization forming electrode; and a reading electrode disposed apart from the writing electrode.

Description

[0001]Japanese Patent Application No. 2005-366925, filed on Dec. 20, 2005, is hereby incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a memory device having a novel structure and operation principle.[0003]As ferroelectric memories utilizing a ferroelectric, a one-transistor (1T) ferroelectric random access memory (FeRAM), a one-transistor one-capacitor (1T1C) FeRAM, and a two-transistor two-capacitor (2T2C) FeRAM have been known.[0004]As the structure of the 1T FeRAM, a metal-ferroelectric-semiconductor (MFS) structure, a metal-ferroelectric-insulator-semiconductor (MFIS) structure, and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure have been known. In FeRAMs having these structures, the amount of drain current at a specific gate voltage is utilized as memory information since the polarization state of the ferroelectric forming a gate insulating film changes the transistor threshold voltage. However, t...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): G11C11/22
CPCG11C11/22H01L28/56H01L27/11507H10B53/30
InventorKIJIMA, TAKESHIHAMADA, YASUAKISHIMODA, TATSUYA
OwnerSEIKO EPSON CORP