Semiconductor memory device

Abstract

A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-282817, filed on Nov. 4, 2008; the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a semiconductor memory device having a three-dimensional memory cell array structure in which electrode layers are stacked to form memory cells densely arranged in the electrode stacking direction.[0004]2. Background Art[0005]Conventional stacked memory technology is based on the structure of layers stacked by repeating for each layer the process of forming normal, planar memory cells on a silicon substrate. This structure is unsuitable for large capacity because it requires many manufacturing steps per layer. In this context, a technique for increasing the capacity with high manufacturing efficiency is proposed (e.g., JP-A-2007-266143(Kok...

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Problems solved by technology

This structure is unsuitable for large capacity because it requires many manufacturing steps per layer.

Depending on the slit pattern layout, there is concern about the problem of short circuit between the word line electrode layers of adjacent blocks or regions across the slit through the residual electrode layers beside the slit.

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