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Semiconductor device and stacked-type semiconductor device

a semiconductor and semiconductor technology, applied in the direction of solid-state devices, printed circuit structure associations, basic electric elements, etc., can solve the problems of reduced rigidity of semiconductor devices, increased warping of csp or bga packages, defective solder joints, etc., to avoid defective solder joints, reduce size and thickness, and prolong the life of solder joints

Inactive Publication Date: 2014-10-07
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach ensures reliable solder joints by maintaining sufficient height and area, reducing the occurrence of defective joints and extending the lifespan of solder joints while avoiding bridging, even at narrow pitches.

Problems solved by technology

However, reducing the thickness of a CSP or a BGA package to meet the demands for size reduction of such apparatuses leads to reduced rigidity of the semiconductor device.
This tends to increase the amount of warping of the CSP or the BGA package due to heating during a solder joining process in a reflow step.
Warping of the CSP or the BGA package causes a gap to form between terminal electrodes of the semiconductor device and board electrodes of the printed wiring board when the semiconductor device and the printed wiring board are joined to each other, causing defective solder joints to occur.
As a result, the gap formed between the solder bumps and the solder paste printed on the printed wiring board becomes larger due to the warping of the CSP or the BGA package.
This leads to a problem in that defective solder joints tend to occur readily.
However, with the aforementioned method in which the diameter of the openings in the resist is gradually reduced, the reduced diameter results in a reduced joint area between the solder bumps and the electrodes.
This results in increased load due to a heating cycle occurring when the power of the semiconductor device is turned on and off.
Moreover, even if the diameter of the openings in the resist is reduced, since the solder bumps formed on the electrodes of the interposer substrate are each formed by surface tension into a spherical shape that is larger in size than the diameter of the corresponding opening in the resist, it is difficult to ensure sufficient height for the solder bumps, resulting in a low effect for reducing the occurrence of defective solder joints between the solder bumps and the board electrodes.
Specifically, with this method, because the solder joint area is small in sections where the warping amount of the interposer substrate is large, the solder joint strength is reduced, and the lifespan of the solder joints is shortened.
However, with the method of the related art in which the supply of solder is gradually increased, the amount of solder is simply increased where the warping amount is large.
Therefore, when the terminals are arranged at a narrow pitch, bridging occurs between the solder bumps, which results in a problem of defective joints different from the aforementioned defective joints.

Method used

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  • Semiconductor device and stacked-type semiconductor device
  • Semiconductor device and stacked-type semiconductor device
  • Semiconductor device and stacked-type semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0016]FIGS. 1A and 1B illustrate a schematic configuration of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1A, a semiconductor device 1 includes a semiconductor element 2 and an interposer substrate 6 with the semiconductor element 2 mounted thereon, and is mounted on a printed wiring board 11, such as a motherboard, serving as a printed wiring board.

[0017]The surface of the interposer substrate 6 on which the semiconductor element 2 is mounted will be defined as a top surface 6a. The top surface 6a is provided with a wire-bonding electrode 4. The semiconductor element 2 and the electrode 4 are connected to each other via a wire 3. The semiconductor element 2, the wire 3, and the electrode 4 are covered with molded resin 7. Although a wire-bonding technique is used for the mounting of the semiconductor element 2 in the first embodiment, a flip-chip technique may be used as an alternative. Furthermore, multiple semiconductor elemen...

first practical example

[0032]Referring to FIGS. 1A and 1B, the openings 8c and 8d of the solder resist 8 that respectively correspond to the electrodes 5c and 5d are given a height of 20 micrometers from the electrodes 5c and 5d. The openings 8b and 8e of the solder resist 8 that respectively correspond to the electrodes 5b and 5e are given a height of 40 micrometers from the electrodes 5b and 5e. The openings 8a and 8f of the solder resist 8 that respectively correspond to the electrodes 5a and 5f are given a height of 60 micrometers from the electrodes 5a and 5f. The solder bumps 9a to 9f formed on the respective electrodes 5a to 5f have a diameter of 300 micrometers. In this case, the height from the surface of each electrode 5a to 5f to the end of the corresponding solder bump 9a to 9f is varied as follows. Specifically, the openings 8c and 8d have a height of 20 micrometers and the solder bumps 9c and 9d have a height of 235 micrometers, the openings 8b and 8e have a height of 40 micrometers and the ...

second embodiment

[0034]Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. 3. In FIG. 3, components that are the same as those in FIGS. 1A and 1B are given the same reference numerals, and descriptions thereof will be omitted. An interposer substrate 6 of a semiconductor device 1A according to the present invention shown in FIG. 3 differs from that in the first embodiment in that the interposer substrate 6 warps upward into a convex shape during a solder joining process (210 to 240 degrees (Celsius)) of the solder bumps 9a to 9f.

[0035]In the semiconductor device 1A, the height of the openings 8a to 8f of the solder resist 8 that respectively correspond to the electrodes 5a to 5f increases with increasing gap distance between the electrodes 5a to 5f and the board electrodes 10a to 10f. In detail, the height of the solder resist 8 is set such that the height of the openings 8a to 8f increases from the periphery of the interpo...

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Abstract

In a semiconductor device according to the present invention, a solder resist has a plurality of openings that expose electrodes. Solder bumps are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate and board electrodes of a printed wiring board on which the semiconductor device is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints.

Description

TECHNICAL FIELD[0001]The present invention relates to semiconductor devices and stacked-type semiconductor devices in which solder bumps serve as external connection terminals.BACKGROUND ART[0002]In the related art, digital apparatuses, including mobile apparatuses, digital cameras, and digital video cameras, have been reduced in size, and semiconductor devices that allow for higher density packaging have been used for mounting components within a smaller space. As examples of such semiconductor devices, chip scale packages (CSPs) and ball grid array (BGA) packages have been widely used. Regarding CSPs and BGA packages, solder bumps serving as external connection terminals are formed at a lower surface of a package in place of lead terminals so that the mounting area can be reduced. By using such CSPs and BGA packages to reduce the area of a printed wiring board, the demands for size reduction of the aforementioned apparatuses can be met. In order to meet the demands for further siz...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L23/48H01L21/48H01L23/00H01L23/13H01L23/31H01L23/498H01L25/065H01L25/10H05K1/14
CPCH01L25/105H01L21/481H01L23/562H01L23/49816H01L2924/15331H01L23/13H01L2225/1058H01L2224/16225H01L23/49822H01L24/48H05K1/144H01L2924/3511H01L2224/73265H01L2924/15311H01L23/3121H01L2224/48091H01L2224/32225H01L2224/48227H01L25/0657H01L24/73H01L2924/00014H01L2924/181H01L2924/00012H01L2924/00H01L2224/45099H01L2224/45015H01L2924/207
Inventor FUJISAWA, YOSHITOMO
Owner CANON KK