System for providing access of multiple data buffers to a data retaining and processing device

Abstract

An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from / to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.

Description

TECHNICAL FIELD OF THE INVENTION[0001]The present disclosure relates generally to systems for providing access of multiple data buffers to a data retaining and processing device and, in particular, to a system for providing access of multiple data buffers to a master device by using I2C protocol for data communication.BACKGROUND OF THE INVENTION[0002]The Peripheral Component Interconnect bus, which is a bus designed by Intel Corporation is a high-speed interface between the central processing unit (CPU) and peripheral devices in a computer system. The bus operates in synchronization with the clock speed of the CPU at 33 Mhz. A customized bus system for a typical high bandwidth server application is a Compact Peripheral Component Interconnect (CPCI) bus.[0003]The CPCI bus is limited to the components that require infrequent access and are subjected to small amount of data transfers, and is therefore not suitable for communication between high-speed integrated circuits.[0004]Conventio...

AI Technical Summary

Benefits of technology

The present patent is about a system that avoids drawbacks caused due to clock pulse stretching in the I2C bus standards. It uses a sequencing means to read and write data to a data retaining and processing device in a plurality of subcycles. The system also includes a direct storage access controller for efficient data read and write operations, and a shifting means for speed efficient access of the data bus to the processing device. The system can use the inter-integrated circuit data transfer protocol to implement serial access of multiple data buffers.

Problems solved by technology

The CPCI bus is limited to the components that require infrequent access and are subjected to small amount of data transfers, and is therefore not suitable for communication between high-speed integrated circuits.

Thus, the IPMI controller cannot emulate a slave to create a multiple slave control system and adds an area overhead to the system.

Further, there is no mechanism to confirm the validity of the data written to the serial memory.

The data has to be read back which is not feasible for time critical applications.

If a single master wants to access multiple data buffers based on the command code communicated, this will increase the software overhead and communication time.

Single buffer I2C peripherals increase software overhead due to software processing for each data received on the bus.

Byte count and memory pointer are maintained by the software increasing the software overhead.

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