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Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism

A technology of analog circuits and extraction methods, which is applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., and can solve the problem of high time complexity of methods

Inactive Publication Date: 2007-11-07
TSINGHUA UNIV
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  • Summary
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

These methods all need a backtracking process when generating symmetric pairs, so the time complexity of the method is relatively high, and the sensitivity method also needs to go through complex sensitivity analysis

Method used

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  • Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
  • Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism
  • Analog circuit layout oriented symmetrical constraint extraction method based on graph isomorphism

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Experimental program
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Embodiment Construction

[0057] The present invention is completed based on the unix workstation Sun v880 of Sun Company.

[0058] Figure 1 is the overall flow chart.

[0059] The devices in the following circuits are MOS transistors M, and the present invention is also applicable to circuits composed of various devices.

[0060] 1. Read the netlist file in Spice format and construct a bipartite graph

[0061] 1) Read the netlist file, and store the device classification into the linked list.

[0062] ●First read the netlist file by line, and judge the nature of the line according to the initial letter of the line:

[0063] ■* indicates a comment line

[0064] The line starting with m / M is the MOS device description line

[0065] The line starting with c / C is the capacitor device description line

[0066] The line starting with r / R is the description line of the resistance device

[0067] ●Read the device name and various parameters in the device description line, and store them in the linked li...

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Abstract

The invention relates to a symmetry constraint extraction of the analog circuit oriented mapping based on the image isomorphism, which belongs to the analog circuit automatically mapping technical field. Its characteristics lie in the following. The connection relationship between the circuit components is represented by the bisection image. Calculate a label value for each node of the image to collectively reflect the topology connection relation between the node and its perimeter ones. When the label values of two nodes are equal, they form a symmetry pair. According to the connection relation between the symmetry pair, determine the symmetry group. The invention eliminates the returning probability when forming the symmetry pair. By this means, it is highly effective and all the symmetry structures of the circuit can be found conveniently.

Description

technical field [0001] A graph isomorphism-oriented symmetry constraint extraction method for analog circuit layout belongs to the field of computer aided design of integrated circuits, especially the field of automatic layout of analog integrated circuits. Background technique [0002] The advancement of semiconductor technology in recent years, especially the emergence of SOC (System on-Chip) technology, has made it possible to integrate digital circuits and analog circuits on the same chip. Since the early 1990s, the digital-analog hybrid integrated circuit market has grown at an annual rate of 15% to 20%. In 2001, this market has exceeded 22 billion US dollars. In the field of digital circuits, there are already quite good CAD tools on the market. However, since analog circuits are very sensitive to nonidealities, higher order effects, and parasitic disturbances (including crosstalk, substrate noise, power supply noise, etc.), analog circuit CAD tools cannot simply bor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50G06F17/30
Inventor 董社勤洪先龙陈松苏毅郝庆生
Owner TSINGHUA UNIV
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