Barrier for capacitor over plug structures

Abstract

An improved barrier stack for reducing plug oxidation in capacitor-over-plug structures is disclosed. The barrier stack is formed on a non-conductive adhesion layer of titanium oxide. The barrier stack includes first and second barrier layers wherein the second barrier layer covers the top surface and sidewalls of the first barrier layer. In one embodiment, the first barrier layer comprises Ir and the second barrier layer comprises IrOx. Above the barrier stack is formed a capacitor.

Description

technical field [0001] The present invention relates to a barrier used, for example, in integrated circuits (ICs), which reduces the diffusion of atoms and molecules such as oxygen. More particularly, the barrier reduces oxidation of the plugs in the capacitors of the plug structure. Background technique [0002] A memory integrated circuit includes a plurality of memory cells interconnected by bit lines and word lines. A memory cell includes a transistor coupled to a capacitor for storing one bit of information. For high-density memory integrated circuits, memory cells use a capacitor-on-plug (COP) structure as shown in Figure 1. The structure includes a capacitor 140 having a dielectric layer 146 disposed between first and second electrodes 141 and 142 . This capacitance is coupled to conductive plug 170 . [0003] Typically, high temperature annealing in an oxygen environment is required to improve the properties of dielectric layers, especially for high-k dielectrics...

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Problems solved by technology

However, as shown, the sidewalls of the barrier and adhesive layers are exposed

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