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A sampling device for analog signal

An analog signal and sampling device technology, applied in signal transmission systems, electrical signal transmission systems, analog-to-digital converters, etc., can solve problems such as poor linearity and achieve high linearity sampling effects

Inactive Publication Date: 2009-02-25
VIMICRO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] It can be seen from the above that when figure 2 When the analog signal sampling circuit shown is sampling, the PMOS transistor is turned on, the voltage potential on the gate is constant at -3V, and the voltage potential on the source is V in , the potential difference between source and gate is (-3-V in ), because the on-resistance of the PMOS transistor is related to the potential difference between the source and the gate, thus causing the sampling signal V output by the analog signal sampling circuit o Poor linearity

Method used

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  • A sampling device for analog signal
  • A sampling device for analog signal
  • A sampling device for analog signal

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Embodiment Construction

[0033] The core idea of ​​the present invention is to set the bias circuit so that the transistor in the sample and hold circuit is in the on or off state within the corresponding time period: when the transistor is in the on state, the potential between the transistor control electrode and the first electrode The difference remains constant and does not change with the change of the input voltage signal, realizing high linearity sampling of the input analog signal; when the transistor is in the off state, it maintains the high linearity sampling signal.

[0034] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0035] image 3 It is a structural schematic diagram of the analog signal sampling device of the present invention, such as image 3 As shown, the device includes a sample-and-hold cir...

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Abstract

The disclosed sampling device for analog signal comprises a sampling hold circuit and an offset circuit to turn on or off transistor in last circuit. Wherein, when turning on the transistor, keeping the potential difference between the control electrode of transistor and the first electrode as constant for high linear sampling; when turning off the transistor, holding the sample signal.

Description

technical field [0001] The invention relates to an analog signal sampling technology, in particular to an analog signal sampling device. Background technique [0002] Sampling an analog signal is a prerequisite for realizing signal digitization. In the prior art, a complementary metal oxide semiconductor (MOS, Metal Oxide Semiconductor), a capacitor, and an operational amplifier are generally used to form a sampling circuit. figure 1 It is a schematic diagram of the basic structure of the existing sampling circuit, such as figure 1 As shown, the sampling circuit includes: four switches sw1, sw2, sw3, sw4, two capacitors C s 、C i And an operational amplifier A, generally, the potential of the reference signal REF is one-half of the high level of the power supply of the operational amplifier A used, and the switch sw1 generally uses a P-channel MOS transistor (PMOS transistor) to effectively prevent the clamping phenomenon from occurring . When the clock signal PH1 is 1 (h...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/12H03M1/34
Inventor 孙涛
Owner VIMICRO CORP