System chip test data compression method of block mark

Abstract

A method for compressing test data of block-labeled system chip utilizes both complete block of data block to be coded and with zero label in compatible to reference data block as well as complete block of data block to coded and with ten label in anti-phase compatible to reference data block simultaneously to dynamically update reference data block in order to increase compatible probability or anti-phase compatible probability of reference data block and data block to be coded.

Description

technical field [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-out self-test (Built-Out Self-Test, BOST) method for a system chip (System-on-a-Chip, SoC). technical background [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory, microprocessor, DSP, etc. This diversified integrated chip has become an integrated system capable of processing various information, which is called System-on-a-Chip, SoC. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited inpu...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

Runlength-based encoding methods include: Golomb codes, FDR codes, EFDR codes, alternate codes, alternate continuous codes and other encoding methods, but these methods all have problems such as complex control protocols; statistics-based encoding methods include: choose Huffman Encoding, variable-length Huffman encoding, but these methods have problems such as high decompression hardware overhead and complicated decoding process; dictionary-based encoding methods include: LZ77, LZ78, LZW, etc., but these methods require large dictionary storage overhead, and at the same time Large number of variable-length indexes complicates decoding

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