Planarising damascene structures

A mosaic structure and planarization technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as depressions and barrier layer erosion

Inactive Publication Date: 2007-10-10
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Disadvantages of CMP processes using low-recessing polishing slurries are that although copper erosion is stopped, barrier erosion may be promoted
According to US 6,376,376 dishing can be a problem where the barrier layer is harder and more chemically stable than copper in a damascene structure (eg where the barrier layer is TaN)

Method used

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  • Planarising damascene structures
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Embodiment Construction

[0034] The present invention will be described with reference to particular embodiments and certain drawings but the invention is not limited thereto but only by the claims. Any reference signs in the claims should not be construed as limiting the scope. The drawings described are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Wherein the term "comprising" used in the present description and claims does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun eg "a", "the", this includes a plural of that noun unless something else is specifically stated.

[0035] Furthermore, the terms first, second and third etc. in the description and claims are used to distinguish between similar elements and do not need to be described as sequential or chronological order. It is to be understood that the terms so used are ...

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PUM

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Abstract

Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarising. During the planarising the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.

Description

technical field [0001] The present invention relates to a method of fabricating a damascene structure for applications such as integrated semiconductor devices, and semiconductor devices fabricated according to said method. Background technique [0002] Currently, damascene interconnect structures are fabricated by CMP (Chemical Mechanical Polishing). The CMP process has been fully described and illustrated by J.M. Steigerwald, S.P. Murarka and R.J. Gutman et al. in "Chemical Mechanical Planarisation of Microelectronic Materials", John Wiley & Sons, New York, 1997. The CMP process involves planarization or polishing by moving the sample surface relative to a polishing pad used to provide support for the sample surface and to carry polishing slurry between the sample surface and the polishing pad to affect the resulting planar surface. Polished. CMP is performed with a liquid polishing slurry. [0003] A damascene structure is a structure embedded in the surface of an exis...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/321H01L21/768
CPCH01L21/76843H01L21/3212H01L21/7684H01L21/76865H01L21/321H01L21/768
Inventor 菲特·恩古耶恩霍安格雷亚·J·A·M·费尔海登
Owner NXP BV
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