Power consumption reduction method for intellectual core and functional module for chip system
A technology of intellectual property cores and functional modules, applied in the direction of data processing power supply, etc., can solve the problems of incomplete power consumption reduction and error-prone, and achieve the effect of reducing jumps, reducing dynamic power consumption, and reducing leakage power consumption
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[0024] Example 1
[0025] As shown in FIG. 1, this embodiment describes a schematic diagram of the power consumption reduction of the original IP core in an explicit state description.
[0026] Step a) Divide all the states of the original IP core into two categories-"idle" state and "working" state, "working" state is not "idle" state, "idle" state is that the IP core is not currently performing effective work status. details as follows:
[0027] In the figure, the box is the working model of the original IP core 10. The status of the original IP core 10 includes "idle", "request", "ready", "running", and "end"; when in the "idle" state, If the bus has no request, it remains in the "idle" state. If the bus sends a request, it enters the "running" state; the circles in the figure indicate the state, and the arrows indicate transitions, indicating the next state of the state machine. The state in the actual circuit of the original IP core 10 is realized by a series of registers (se...
Example Embodiment
[0036] Example 2
[0037] FIG. 2 is a schematic diagram of reducing power consumption of an original IP core describing an implicit state in another embodiment of the present invention, and illustrates a specific method for low-power transformation. The pipeline originally designed for this IP core is divided into 3 stages, each stage is a register slot containing many register bits. The method for reducing power consumption in this embodiment includes:
[0038] Step a) Divide all the states of the original IP core into two categories-"idle" state and "working" state, "working" state is not "idle" state, "idle" state is that the IP core is not currently performing effective work status.
[0039] One feature of the original IP core of this embodiment that is different from most IP cores is that there is no explicit state machine description in the design code described in the hardware description language, and its state is implicitly represented by the effective bits of the multi-s...
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