Power consumption reduction method for intellectual core and functional module for chip system

[0024] Example 1

[0025] As shown in FIG. 1, this embodiment describes a schematic diagram of the power consumption reduction of the original IP core in an explicit state description.

[0026] Step a) Divide all the states of the original IP core into two categories-"idle" state and "working" state, "working" state is not "idle" state, "idle" state is that the IP core is not currently performing effective work status. details as follows:

[0027] In the figure, the box is the working model of the original IP core 10. The status of the original IP core 10 includes "idle", "request", "ready", "running", and "end"; when in the "idle" state, If the bus has no request, it remains in the "idle" state. If the bus sends a request, it enters the "running" state; the circles in the figure indicate the state, and the arrows indicate transitions, indicating the next state of the state machine. The state in the actual circuit of the original IP core 10 is realized by a series of registers (sequential circuit), and the transition is realized by a combinational circuit. Since there is an explicit state machine description in the hardware description language in this embodiment, the state of the original IP core 10 is directly divided into two categories—"idle" state and "working" state. The "working" state is represented by " It constitutes a state other than the "idle" state.

[0028] b) Provide a logic circuit connected with the original IP core to form a new low-power IP core. The logic circuit completes the following logic functions: if the bus has no request for the original IP core, keep the clock off; The request of the IP core turns on the clock of the original IP core, and the original IP core enters the "working" state; keep the clock on until the original IP core is in the "idle" state and there is no bus request, turn off the original IP core clock and keep it off, Until the bus makes a request for the IP again.

[0029] details as follows:

[0030] The original IP core 10 needs to introduce a working clock from outside. Before the working clock signal enters the original IP core 10, a logic circuit 11 (in the dashed box in the figure) is added. The logic circuit 11 includes:

[0031] The NAND gate circuit 12, the two input ends of the NAND gate circuit 12 are respectively connected to the "idle" state flag signal of the original IP core 10 and the bus unrequested flag signal.

[0032] The latch 13, the output terminal of the NAND circuit 12 is connected to the data input terminal of the latch 13, and the other input terminal (clock input terminal) of the latch 13 is connected to the working clock signal, the latch 13 The output terminal of the AND circuit 14 is connected to one input terminal, the other input terminal of the AND circuit 14 is connected to a working clock signal, and the output terminal of the AND circuit 14 is connected to the original IP core 10 for its input working clock signal.

[0033] When the original IP core 10 meets the two conditions indicated by the dashed line in Figure 1, the clock of the IP core is turned off, otherwise the clock is kept on, that is, if the bus does not request the original IP core, the clock is kept off; if the bus has a pair The request of the IP core turns on the clock of the original IP core, and the original IP core enters the "working" state; keep the clock on until the original IP core is in the "idle" state and there is no bus request, turn off the original IP core clock and keep it off , Until the bus makes a request for the IP again.

[0034] It can be seen that this embodiment adds a logic circuit on the basis of the original IP core 10 and implements the clock switch logic to form a new IP core, which is a low-power IP core 15, which automatically switches the entire IP core 15 in real time. The clock reduces the jump of the IP core 15 clock network, thereby reducing the dynamic power consumption of the IP core 15.

[0035]Further, the power supply of the logic circuit 11 is isolated from the power supply of the original IP core 10. The logic circuit 10 also implements the following logic functions: if and only if the original IP core 10 is in the "idle" state and there is no bus When requested, the power supply of the original IP core 10 is turned off; otherwise, the power supply of the original IP core 10 is turned on. Such a low-power IP core 15 can automatically switch the power supply of the original IP core 10, and reduce the leakage power consumption of the IP core without affecting normal operation.

[0036] Example 2

[0037] FIG. 2 is a schematic diagram of reducing power consumption of an original IP core describing an implicit state in another embodiment of the present invention, and illustrates a specific method for low-power transformation. The pipeline originally designed for this IP core is divided into 3 stages, each stage is a register slot containing many register bits. The method for reducing power consumption in this embodiment includes:

[0038] Step a) Divide all the states of the original IP core into two categories-"idle" state and "working" state, "working" state is not "idle" state, "idle" state is that the IP core is not currently performing effective work status.

[0039] One feature of the original IP core of this embodiment that is different from most IP cores is that there is no explicit state machine description in the design code described in the hardware description language, and its state is implicitly represented by the effective bits of the multi-stage pipeline , So it needs to be handled appropriately, as follows:

[0040] First, monitor the instruction of the bus 21 outside the original IP core 20 (inside the dashed box in the figure) to determine whether it is a valid request. If it is, the "request" signal is set to 1, otherwise it is set to 0; use the pipeline 1 stage 22 When the first clock rising edge arrives after the "request" signal is set to 1, set the effective bit to 1, that is, the "pipeline 1 stage effective" signal is 1; the subsequent two-stage pipeline, pipeline The second stage 23 and the third stage 24 of the pipeline each contain a valid bit register. The value of the effective bit register of the first stage 22 of the pipeline is transferred to the effective bit of the second stage 23 of the pipeline in the next cycle, and the effective bit of the second stage 23 of the pipeline is transferred in the next cycle. Give the valid bits of the 3rd stage 24 of the pipeline, and so on; use the valid bits of the 1st to 3rd stages of the pipeline as the input of the first OR circuit 25, and output the "pipeline busy" signal; combine the "request" signal and "pipeline busy" The signal is used as the input of the second OR circuit 26, and the output is a "clock enable" signal, which is input as the data terminal of the low-level active latch 27, and an external clock signal is input as the clock terminal of the latch 27, The output of the latch 27 is a “gated” signal, and the signal and the clock signal are used as the two input ends of the AND circuit 28, and the output is the clock used internally by the original IP core 20.

[0041] The first OR gate 25 has three inputs, the second OR gate 26 has two inputs, and the AND gate 28 has two inputs.

[0042] Since the "clock enable" signal is constructed by a combinational circuit, in order to avoid possible clock glitches (glitch) that may cause the IP core to work incorrectly, a latch (Latch) 27 and an AND circuit 28 are used to build the gating unit: When the level is high, the latch 27 is closed to shield the transmission of the glitch; when the clock is low, the latch 27 is turned on, and the AND gate 28 will shield the transmission of the glitch.

[0043] In this embodiment, a logic circuit is added on the basis of the original IP core 20 and the clock switch logic is implemented to form a new IP core 30. This core is a low-power IP core 30 and has the same logic functions and functions as the original IP core. Timing can automatically switch the clock of the entire IP core in real time, reducing the jump of the IP core clock network, thereby reducing the dynamic power consumption of the IP core.

[0044] Further, the original IP core 20 is isolated from the power supply of other logic circuits, and the "gating" signal or clock enable signal output by the latch 27 is used as the power switch signal of the IP core 20, when the "gating" signal When it is 1, the power of the IP core 20 is turned on, and when it is 0, the power of the IP core 20 is turned off. In this way, the low-power IP core 30 can automatically switch the power supply of the original IP core 20, and reduce the leakage power consumption of the IP core 20 without affecting the normal operation.