Semiconductor device and fabrication process thereof

Abstract

A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film,an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat bottom surface, and the barrier metal film has a larger film thickness at the tip end part of the via-plug as compared with a sidewall surface of the via-plug.

Description

[0001] Cross References to Related Applications [0002] This application is based on a prior Japanese Patent Application No. 2006-254426 filed on September 20, 2006, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device with a multilayer interconnection structure and a manufacturing method thereof. Background technique [0004] Current semiconductor integrated circuit devices employ a multilayer interconnection structure called a damascene or dual damascene structure, in which a low-resistance Cu interconnection pattern is embedded in a low-K interlayer insulating film to connect a large number of semiconductor elements formed on a substrate. [0005] For a multilayer interconnect structure of a damascene or dual damascene structure, interconnect grooves or contact holes are formed in an interlayer insulating film of a low-K...

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Problems solved by technology

[0018] When such a device isolation trench 15A is filled with a Cu interconnection pattern in a state where the barrier metal film 16 is incompletely formed, it causes diffusion of Cu from the Cu interconnection pattern 15B into the interlayer insulating film 13, and causes problems such as short circuit or film peeling. And other issues

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