Semi-conductor memory device and manufacturing method thereof
A technology for storage devices and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as the inability to use high-density memory, excessive flash memory unit area, etc., to avoid excessive unit area Large, avoiding the effects of low storage efficiency and reduced unit area
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[0045]A layout diagram of an embodiment of the semiconductor memory device of the present invention is shown in FIG. 2A. As shown in FIG. 2A, at least one memory cell pair is distributed, and each memory cell pair includes a memory cell 200a and a memory cell 200b. The memory cell pairs are arranged serially in XX', that is, the bit line direction, and each memory cell pair is distributed with the selection gate 204 of the memory cell 200a along the bit line direction, sharing the control gate 207 and the selection gate 204 of the memory cell 200b, Wherein the selection gates 204 of the memory cells 200a, 200b are symmetrical about the common control gate 207; the memory cell pairs are arranged in parallel in the YY' direction, that is, the word line direction, and the select gates 204 and the common control gate 207 of the adjacent memory cell pairs share a common Line-aligned distribution, parallel to the Y-Y' axis. Adjacent memory cell pairs in the X-X' and Y-Y' directions ...
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