Pattern shielding structure for dry etching and method thereof

Abstract

The present invention proposes a 3D electronic packaging structure with enhanced grounding performance and embedded antenna, and the packaging unit can achieve multi-chip stacking through the signal contacts on the top and bottom surfaces of the unit. A single or multiple grounding layers are on the back of the substrate in the packaging unit to facilitate the grounding for the semiconductor element; further, the packaging unit is applicable to a wafer level packaging process, so the manufacturing cost of each individual packaging unit is reduced. The above grounding layers are also the signal transmission paths of the electronic elements in the packaging structure of the invention, and a single or multiple via holes around the electronic element layers allow electrical signal connection between the top and bottom surfaces of the packaging structure, and thus enable more functionality in the packaging unit. Moreover, the grounding layers may have circular signal channels to construct a 3D stacked packaging structure with embedded antenna.

Description

technical field [0001] The present invention relates to an electronic packaging structure, especially a three-dimensional stacked packaging unit with enhanced grounding characteristics and embedded antennas. The telecommunication contacts on both sides of the packaging unit achieve the purpose of multi-chip stacking. Background technique [0002] Today's electronic products are mostly aimed at miniaturization, high performance, high precision, high reliability, and high responsiveness, etc., so that the distribution density of circuit components is too high, and the volume of the circuit is greatly reduced. However, the circuits of electronic products are more delicate. There will be more and more components formed in a small space, so the chance of mutual telecommunication interference will increase, affecting the stability of electronic product signals; among them, electromagnetic interference (Electromagnetic Interference, EMI) and noise are the most common problems. The...

AI Technical Summary

Problems solved by technology

This patent mainly uses a plurality of via holes 206 to be formed in the chip, and at the same time, a metallization line 204 is laid on the hole wall, and a fixed structure 205 with conductive properties is used, so it can effectively shorten the telecommunications transmission path between chips and reduce signal noise. Although the packaging structure can shorten the transmission path between chips, due to the increase in the distribution density of integrated circuit chips, the chances of telecommunication interference between different types of chips will increase, which will affect the stability of electronic product signals

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