Grids structure and method of manufacture

Abstract

A method for manufacturing a gate structure comprises the steps as follows: a first dielectric layer is formed on a semiconductor substrate and a gate layer is deposited; the gate layer covers the first dielectric layer and the gate layer is etched; a second dielectric layer is deposited and the second dielectric layer covers the gate layer; a third dielectric layer is deposited and the third dielectric layer covers the second dielectric layer; the third dielectric layer is etched and the second dielectric layer is etched adopting the wet method, and the third dielectric layer is removed; a side wall is formed combining the dry method with the wet method, and different dielectric materials are selected as the first dielectric layer and the second dielectric layer; the removal of the dielectric layer step by step can be realized by selecting the etching solution having high etching selection ratio over the first dielectric layer and the second dielectric layer without causing the damage to the gate oxide layer before the source drain is formed.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a gate structure and a manufacturing method thereof. Background technique [0002] figure 1 In order to illustrate the structural schematic diagram of the gate structure in the prior art, such as figure 1 As shown, the current gate structure is usually formed by first forming a gate oxide layer 11 on the semiconductor substrate 10 , and then forming a gate 13 and sidewalls 12 surrounding the gate on the gate oxide layer. For a semiconductor device including multiple gate structures, seams exist between adjacent gate structures. In the current integrated circuit manufacturing process, semiconductor devices are formed by alternately depositing interconnected interlayer dielectric layers and metal layers after forming gate structures. [0003] However, it has been found in actual production that when the first interlayer dielectric layer, ie, the Pre-Meta...

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Problems solved by technology

When this method is applied to the process of depositing PMD layers, that is, when utilizing HDP with simultaneous deposition-sputtering ability to deposit PMD layers or utilizing deposition-etching-deposition process to deposit PMD layers, as the device size decreases gradually, for To ensure that the PMD layer fills the gaps between the gate structures without holes, the control of deposition, sputtering / etching process parameters becomes more stringent, and it is increasingly difficult to achieve

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