Semiconductor integrated circuit

Abstract

An object of the present invention is to provide a semiconductor integrated circuit including a plurality of cell blocks respectively configured with standard cells having different cell heights and capable of reducing clock skew between the cell blocks, the semiconductor integrated circuit comprising A first standard cell and a second standard cell different in cell height from the first standard cell, a pair of N-type diffusion regions and a first substrate for providing the first standard cell are arranged in the P well region of the first standard cell The P-type diffusion region of the power supply, a pair of N-type diffusion regions and the P-type diffusion region for providing the second substrate power supply to the second standard cell are arranged in the P well region of the second standard cell, and the N-type diffusion region of the first standard cell The distance between the N-type diffusion region and the P-type diffusion region is substantially the same as the distance between the N-type diffusion region and the P-type diffusion region of the second standard cell.

Description

technical field [0001] The present invention relates to a standard cell type semiconductor integrated circuit in which standard cells having different cell heights are mixed. Background technique [0002] In a standard cell type semiconductor integrated circuit, generally, the height of each cell (cell height) is designed to be uniform, as shown in FIG. 1 , in order to arrange standard cells at high density without voids. FIG. 1 shows a plan view of a design example of a cell block 1101 including standard cells 1102 of a plurality of columns (four columns in FIG. 1 ). Here, the cell height of each standard cell 1102 refers to the height of the standard cell 1102 in the direction (Y-axis direction in FIG. 1 ) perpendicular to the column direction (X-axis direction in FIG. 1 ), which is the direction in which the standard cells 1102 are arranged. The dimensions of the unit, the height of this unit is represented by the symbol H in Figure 1. [0003] When aiming at high integ...

AI Technical Summary

Problems solved by technology

In the case of supplying a clock signal with CTS in a plurality of cell blocks having different cell heights, since transistors arranged in standard cells having different cell heights have different sizes, there is a problem that the characteristics of these transistors become different from each other. Same, with increased clock skew

[0015] For this reason, the problem that occurs in the conventional embodiment described in the above-mentioned Patent Document 1 is that due to the cell height of the standard cell, the distance between the diffusion regions in the standard cell, and the grid in the standard cell of different columns The distance between the electrodes is different, therefore, the delay characteristics of the transistors are different, and the clock skew increases

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