Optimization method of multi-level gating clock network in nanotechnology

Abstract

The invention belongs to the technical field of electrons and relates to a multistage gated clock network optimization method in a nanometer technology; the method comprises the steps of assuming that a network has N stages of gated clocks, Kn gated clock units exist in the nth stage, degrading nth-grade gated clocks, wherein n is larger than 1, and the degrading steps are as follows: (1) finding out all 2nd-stage gated clocks in a circuit, a total of K2; (2) for K2 gated clock units in the 2nd stage, disconnecting the clock ends of the K2 gated clock units, and respectively connecting with clock root nodes; (3) for the K2 gated clock units in the 2nd stage, adding corresponding logic gate groups at the enable ends of the K2 gated clock units, connecting an enable signal in an original circuit to input ends of the logic gate groups, and connecting output ends of the logic gate groups to input ends of the gated clock units; (4) combining K2 logic gate groups; (5) repeating the operation process of the step (1) to (4), and sequentially combining a 3rd-grade gated clock structure, a 4th-grade gated clock structure, and so on, and an Nth-grade gated clock structure into a 1st-stage gated clock structure to complete the optimization of a gated clock network.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a multi-level gating clock network optimization method under nanotechnology. Background technique [0002] Under the nanometer process, the reduction of the transistor feature size puts forward more stringent requirements on the manufacturing process, and various effects that could be ignored before are becoming more and more prominent. Among them, the impact of process, voltage and temperature on the performance, function and stability of the chip is becoming more and more obvious. In order to ensure that the manufactured chip can adapt to various working environments, it is necessary to take the possible impact into consideration during the design process, that is, consider the influence of process, voltage and temperature on the delay of cells and interconnect lines when performing static timing analysis , the specific operation process is mainly divided into t...

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Problems solved by technology

However, the mesh clock structure is also only suitable for relatively simple clock structures with no gating clock or only one level of gating clock

[0011] The above methods all increase the proportion of the common path of the clock to varying degrees, but they are only applicable to a clock structure with a single structure, and the design effect for multi-level gated clocks is limited.

However, with the development of the microelectronics industry, the design of multi-level gated clocks is becoming more and more common, and how to reduce the clock skew and its uncertainty of such designs has become more and more difficult

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