Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region, and a contact which contacts with the channel region.

Description

[0001] Cross-references to related applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2007-017115 filed on January 26, 2007, the entire contents of which are incorporated herein by reference. Background technique [0003] Demand for small, high-capacity nonvolatile semiconductor memory devices is rapidly increasing, and NAND-type flash memory that can achieve high integration and large capacity has attracted attention. However, in order to achieve miniaturization, finer processing of wiring patterns and the like is required, and miniaturization of design rules has become increasingly difficult. Therefore, in recent years, semiconductor memory devices in which memory cells are three-dimensionally arranged have been proposed many times in order to increase the degree of integration of memories. [0004] However, in a conventional semiconductor memory device in which memory cells are three-dimensionally arranged, the...

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Problems solved by technology

[0005] Due to the above structure, when carriers are accumulated in the channel region of the memory cell or the selection gate transistor, the threshold value of the channel region changes, and the operation becomes unstable, etc.

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