Analog switch chip design method and chip device

Abstract

The invention provides a design method of an analog switch chip which controls the time sequence by a clock circuit and controls the work of the substrate bias canceling circuit of a main switch MOS in a standard CMOS technique analog switch circuit by an additional switch module. The invention also provides a chip device which comprises a standard CMOS technique analog switch circuit, a substrate bias canceling circuit, an additional switch module and a clock circuit. The substrate bias canceling circuit is connected with the substrate of the main switch MOS; a secondary switch provided by the additional switch module is respectively connected with the substrate bias canceling circuit and a power supply voltage; the clock circuit provides a chip device control time sequence. The analog switch chip of the invention improves the bandwidth of the analog switch as well as the turn-off isolation and charge injection properties of the analog switch, which simultaneously ensures the substrate bias effect to be cancelled and improves the conducting impendence property.

Description

Technical field [0001] The invention relates to the field of chip design, in particular to a method and device for designing an analog switch chip. Background technique [0002] In the standard CMOS process, the ideal working state of MOS always assumes that the source region and the substrate are grounded together, that is, Vbs is equal to 0, but in actual working states, the substrate and the source are often disconnected, and Vbs is not equal to 0. It can be known from the basic PN junction theory that the depletion layer of the PN junction in the reverse bias will expand. In addition, the substrate bias Vbs will have a series of effects on the characteristics of the MOSFET. In order to ensure the direction bias of the PN junction between the source-substrate and the drain-substrate, for n-channel devices, the substrate is usually connected to a negative bias. For p-channel devices, the substrate is positively biased, or the MOS substrate and the source region are directly sho...

AI Technical Summary

Problems solved by technology

[0003] The performance indicators of the analog switch chip mainly include on-resistance, bandwidth, off-isolation, and charge injection. Currently, under the standard CMOS process, the technology of eliminating the substrate bias effect of the analog switch basically adopts certain circuit architectures to realize the PMOS tube lining. The selection of the bottom voltage can eliminate the lining offset effect and improve the on-resistance performance. However, due to the mutual constraints of the four properties, there are few methods that can simultaneously improve the bandwidth and turn-off of the analog switch on the premise of ensuring the on-resistance performance. break isolation and charge injection performance

Because the offset elimination circuit is externally connected to the PMOS, as shown in the attached figure 1 , using the line offset elimination circuit, select the largest of the input and output voltages as the PMOS substrate, which is equivalent to connecting a capacitor in series at both ends of the main switch MOS, which will seriously limit the off-isolation performance of the analog switch. and affect its operating bandwidth

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