Leadframe and flip chip type semiconductor package using leadframe as chip supporter

Abstract

The invention discloses a flip chip semiconductor encapsulating part which takes a lead frame as a chip bearing part and comprises a chip electrically connected to the lead frame by solder bumps in a flip chip way, and an molding colloid which encapsulates the chip, the solder bumps and the lead frame, wherein, the lead frame is composed of a plurality of leads and a ground plane positioned among the leads, a slit is formed on the ground plane, a molding compound used for forming the molding colloid can be filled in the slit, thereby the associativity between the ground plane and the molding colloid is promoted and the relamination of the junction surface between the ground plane and the molding colloid in the subsequent temperature cycle can be avoided so as to enhance the dependability of the finished product.

Description

technical field [0001] The invention relates to a flip-chip semiconductor package technology, in particular to a flip-chip semiconductor package with a lead frame as a chip carrier and the applied lead frame. Background technique [0002] The traditional FCQFN (Flip Chip Quad Flat Non-Leaded) semiconductor package is as follows figure 1 In the shown structure, a chip 11 is placed on a lead frame 12 through a plurality of solder bumps 10 in a flip-chip manner, so that the chip 11 and the lead frame 12 form an electrical connection relationship; the chip 11, the lead frame 12 and solder bumps 10 are coated with an encapsulant 13, and after the encapsulant 13 is formed, the side surfaces (SideSurface) 120a and bottom surface (Bottom Surface) 120b (Bottom Surface) 120b of each lead 120 of the lead frame 12 are exposed. The encapsulant 13, and make the bottom surface 120b of each lead 120 flush with the bottom surface 13b of the encapsulant 13, so that the guide pin 120 of the p...

AI Technical Summary

Problems solved by technology

Although the semiconductor package 2 has a large ground plane 221 to improve electrical properties and heat dissipation efficiency, the ground plane 221 only has its side 221a and part of the top surface 221b combined with the encapsulant 23, so that the ground plane 221 and the package The bonding between the colloids 23 is insufficient, and it is easy to make the ground plane 221 and the encapsulation colloid 23 between the ground plane 221 and the encapsulation colloid 23 due to the difference in coefficient of thermal expansion (CTE Mismatch) between the materials of the ground plane 221 and the encapsulation colloid 23 in the subsequent thermal cycle (Thermal Cycling). Delamination of the joint surface occurs, such as Figure 2C As shown in D in the figure; once delamination occurs, it will lead to the intrusion of water vapor and the Popcorn Effect, which will affect the reliability of the semiconductor package 2

In addition, due to the large area of ​​the ground plane 221 , greater thermal stress will be generated during the thermal cycle, which will more easily lead to the delamination of the ground plane 221 and the encapsulant 23

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