Semiconductor memory device and its manufacture method

Abstract

Self-aligned polysilicon process is implemented on a common source polar line to reduce the surface resistance and the contact resistance, thereby improving the unit current characteristics. Therefore, the size of the chip is reduced and the chip of each wafer is increased, thereby obtaining high yield. In addition, the structure limit of a flash unit is overcome when a semiconductor storing device is integrated highly and reduced.

Description

[0001] This application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2007-0050823 (filed May 25, 2007), the entire contents of which are hereby incorporated by reference. Background technique [0002] A self-aligned source process may generally be used to form source lines of semiconductor memory devices. In the self-aligned source process, after the stacked gate structure is formed, the cell area excluding the common source part can be covered with a photosensitive film, the device isolation film of the source line part can be removed by etching, and ionization can be performed. implanted to form a common source line. [0003] as in the exemplary figure 1 and Figure 2A As illustrated in , device isolation film 12 may be formed on and / or at a device isolation region over semiconductor substrate 11 . A trench oxide film 13 and a first polysilicon film 14 may be sequentially formed on and / or over the entire structure, and then patterned by a photol...

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Problems solved by technology

Therefore, cell current characteristics may be degraded

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