Modulation data conversion unit and modulation data conversion method

Abstract

The invention discloses a modulating data converter and a modulating data conversion method. The modulating data converter comprises a parallel data processing module for receiving modulating data, converting the modulating data received in each clock period according to the method engaged with the receiver into the parallel data of N bit width to be sent, wherein N is not lower than the possiblemaximum bit width of the modulating data; a but serializer / deserializer SERDES of clock embedding type receiving and converting parallel data into serial data to be output. The invention adopts serial bus to replace parallel bus, to realize higher data transmission rate, and the invention can reduce data lines and hardware by changing the parallel data into serial data, thereby reducing the area of a modulator. And the adopted synchronous clock is generated by the SERDES and is not attained by the engagement to provide convenient application.

Description

technical field [0001] The invention relates to the communication field, in particular to a modulation data conversion unit and a modulation data conversion method. Background technique [0002] In the current digital TV modulator industry, the transmission method of parallel data plus synchronous clock is commonly used, such as figure 1 As shown; in general, data and clocks are transmitted using differential LVDS signals, and data can be synchronized with the rising or falling edge of the clock. [0003] For the I (in-phase) Q (quadrature phase) modulator, both I and Q data use the same interface. For example, in the modulator of the CMMB system, the parallel data bit width of one channel is 16 bits, plus a clock bit A total of 17 bits, so physically the two IQ channels need to use IDC40 sockets, which occupy a large board area; in addition, because each bit of data and clock requires a low-voltage differential signal LVDS transmission unit, a large number of hardware impl...

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Problems solved by technology

[0003] For the I (in-phase) Q (quadrature phase) modulator, both I and Q data use the same interface. For example, in the modulator of the CMMB system, the parallel data bit width of one channel is 16 bits, plus a clock bit A total of 17 bits, so physically the two IQ channels need to use IDC40 sockets, which occupy a large board area; in addition, because each bit of data and clock requires a low-voltage differential signal LVDS transmission unit, a large number of hardware implementations are required. At the same time, it also needs a large number of DAC (digital / analog conversion) boards for the receiving unit, which is expensive and not easy to use; moreover, it needs to be agreed to use the rising edge or falling edge of the clock, but in the synchronization process Transformation is possible, so there is a speed limit on data transfer

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