Semiconductor testing apparatus and semiconductor memory testing method

Abstract

A testing apparatus for testing a tested memory having a block function that can rewrite data for each of blocks each consisting of a plurality of pages each consisting of a plurality of bits. The testing apparatus comprises a pattern generating part (ALPG) that produces the address information of a page and generates a testing pattern; a waveform shaping part (FC) that shapes the testing pattern to output a testing signal based on the testing pattern; a comparing part (LC) that compares a resultant signal outputted by the tested memory with an expected value; and a bad block memory (BBM) that stores information of faulty blocks of the tested memory in advance and that, if the page specified by the address information is included in a faulty block, outputs a faulty signal to be used for skipping from that address information to the address information of a page included in a tested block next to the faulty block.

Description

technical field [0001] The present invention relates to a semiconductor test device, for example, to a semiconductor test device for testing a data storage type memory rewritable in blocks such as a NAND flash memory. Background technique [0002] The semiconductor memory test device includes: a timing generator, a pattern generator, a waveform shaper and a logic comparator. The timing generator generates a periodic clock and a delay clock based on timing data designated by a timing setting signal (hereinafter referred to as a TS signal) output from the pattern generator. The pattern generator outputs the test pattern data given to the memory under test (MUT (Memory Under Tester)) according to the periodic clock from the timing generator. The test mode data is given to the waveform shaper, and the waveform shaper uses the delayed clock to shape the waveform at the timing required for the test, and applies the shaped test signal to the memory under test. The resulting signa...

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Problems solved by technology

[0004] However, although writing to a bad block and comparison of the resulting signals are prohibited, access to each page within the bad block is still performed

Each access time is shorter than the usual test time for a good block, but quite time consuming since the access is performed for each page within a bad block

[0005] In particular, the capacity of NAND-type flash memory has doubled every year in recent years, so the test time associated with this has also tended to increase

So, accessing unwanted bad blocks will result in increased test cost

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