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Processor system, bus controlling method, and semiconductor device

A technology of processor system and virtual processor, which is applied in the direction of electrical digital data processing, instruments, computers, etc., can solve the problems of large performance estimation error, deterioration of CPU core performance, and affecting system performance, so as to achieve equalization and access performance effect

Inactive Publication Date: 2008-12-17
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this time, although the impact of the shared bus is considered for the access performance of the bus, if the impact is not equally distributed to the two CPU cores, the error in performance estimation will be large.
In addition, the performance of only a single CPU core deteriorates, affecting system performance
[0024] That is, in a multiprocessor system, the bus access performance cannot be estimated with high precision
[0025] In addition, even in a multi-threaded processor, the same problem as the above-mentioned multi-processor occurs, and sometimes it is desired to prevent the performance of bus access from being biased only to a specific thread.

Method used

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  • Processor system, bus controlling method, and semiconductor device
  • Processor system, bus controlling method, and semiconductor device
  • Processor system, bus controlling method, and semiconductor device

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Experimental program
Comparison scheme
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Embodiment approach 1

[0123] Embodiment 1 of the present invention will be described. The processor system in this embodiment is configured to limit the number of consecutive executions of the transfer phase corresponding to the plurality of access requests to the maximum when a plurality of access requests are continuously issued without leaving a predetermined period of time from one master unit. N times. Here, the "predetermined period" is a period corresponding to part or all of the period from when the access request issued immediately before is accepted to when the transfer phase of the access request is completed. Thereby, access performance among master units can be evenly distributed.

[0124] FIG. 4A is a configuration diagram showing a processor system in Embodiment 1 of the present invention. The processor system of FIG. 4A includes a multiprocessor 4-1 and a shared memory 4-24. In Embodiment 1, it is assumed that the multiprocessor 4-1 mounts two processor units (PU0, 1) as a plural...

Embodiment approach 2

[0179] Embodiment 2 of the present invention will be described. FIG. 7A is a system configuration diagram of Embodiment 2. FIG. In this embodiment, control is performed to allow continuous access from the same processor only for a certain set period. Parts that can be explained in the same way as in FIG. 4A are assigned the same symbols, and explanations thereof are omitted.

[0180] Compared with FIG. 4A, the bus IF part 4-10 of FIG. 7A increases the suppression cycle counter 7-1 which counts the predetermined number of cycles, and the suppression cycle setting register which can set and hold the predetermined number of cycles from any master unit. 7-4. The suppression cycle counter 7-1 is counted down after loading the cycle number set in the suppression cycle setting register 7-4, for example.

[0181] Each time an access request is accepted, the reception control unit 411 validates the flag information, sets identification information corresponding to the access request...

Embodiment approach 3

[0190] Embodiment 3 of the present invention will be described. FIG. 8A is a system configuration diagram of the third embodiment. In the present embodiment, control is performed to suppress a certain number or more of consecutive bus accesses from the same processor. The bus IF part 4-10 of Fig. 8A is compared with Fig. 4A, and the difference lies in increasing the continuous number permission register 8-5 that can set and keep the number of times N of continuous transmission from any master unit, and the continuous number of counts. Counter 8-1. The consecutive number counter 8-1 counts down after loading the N held in the consecutive number permission register 8-5, for example. Parts that can be explained in the same way as in FIG. 4A are assigned the same symbols, and explanations thereof are omitted.

[0191] Figure 8B It is a flowchart showing an example of the reception control processing in the reception control unit 412 . Figure 8B Compared with Fig. 4B, the di...

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Abstract

Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU 0 and PU 1 each of which issues an access request for accessing the shared memory, a bus IF unit 4 - 10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4 - 10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N. The bus control method and the semiconductor are also provided.

Description

technical field [0001] The present invention relates to a processor system called a multiprocessor equipped with a plurality of processors, and a bus control method for such a processor system. Background technique [0002] When a multiprocessor equipped with multiple processors accesses the shared memory via the shared memory bus, if a large number of bus accesses occur from one processor and the priority of the processor is set high, it will be difficult to accept Access requests from other processors. [0003] As a prior art, for the same problem when a plurality of bus masters access a shared bus, there is a method of monitoring the access frequency from each bus master and changing the priority during mediation (refer to Patent Document 1 ). [0004] According to this technique, by monitoring the access status from each bus master during a certain period of time, and setting the priority of the bus master with a large number of access times for each of the certain per...

Claims

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Application Information

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IPC IPC(8): G06F13/36G06F15/167
Inventor 金子圭介山本崇夫山崎雅之桧垣信生藏田和司中西龙太
Owner PANASONIC CORP
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