Manufacturing method of multi-chip type multilayered capacitor

Abstract

The present invention provides a production method of a multi-chip typed multilayer capacitor, which has simple production process, low cost, convenient assembly and high qualification rate. The production method of the invention is characterized by comprising the following steps: different metal sheet base plates are respectively cut into a plurality of separated anode strips and cathode strips, the extension part of which are still connected with the base plates: after being punched out a through hole which is corresponding to and smaller than the cathode strips and the anode strips, a separated sheet with multiple pores is used as an isolating layer between the cathode strips and the anode strips; and then the cathode strips, the anode strips and the isolating layer are stacked and pressed in order of the cathode strip, the isolating layer, the anode strip, the isolating layer and the cathode strip to form at least one layer of laminated structure of the cathode strip, the isolating layer and the anode strip; and then the laminated structure is dipped in an electrolyte solution to absorb electrolytes, and thermally polymerizing is carried out to cause the isolating layer between the anode strips and the cathode strips to form a macromolecule polymer electrolyte layer with electrical conductivity; finally the laminated structure is cut to derive an anode guide plate and a cathode guide plate, and then the multi-chip typed multilayer capacitor is completed.

Description

technical field [0001] The invention relates to the technical field of capacitors, in particular to a manufacturing method of multi-element chip-type multilayer capacitors. Background technique [0002] Due to the evolution of semiconductor technology, more sophisticated and advanced electronic components have been continuously developed under the increasing market demand for semiconductor-structured products. As far as the current semiconductor technology is concerned, such as flip-chip technology, design of laminated substrates, and design of passive components, etc., all occupy an indispensable position in the semiconductor industry. Taking the flip chip / ball array package structure as an example, the chip is arranged on the surface of the package substrate, and the chip and the package substrate are electrically connected, and the package substrate is a multi-layer patterned circuit layer, and a multi-layer insulating layer The patterned circuit layer can be defined by ...

AI Technical Summary

Problems solved by technology

However, if a capacitor wants to increase its capacitance value, it must be connected in parallel to stack several capacitors and add the capacitance values ​​of these capacitors to obtain a larger capacitance value after adding several capacitance values ​​(as shown in Figure 2 shown), and the stacked aluminum chip capacitor 7 is packaged 9, and the lead pins 8 are drawn from the anode 1 and the cathode end respectively to form a complete capacitor. However, the stacked capacitor needs to be squeezed by the jig 11. As shown in Figure 3), the manufacturing process is complicated (addition of procedures such as clamping with jig 11 and applying silver glue 10), high cost, high short-circuit rate, and easy thermal stress during packaging to cause capacitor damage, as in the United States. The No. US6421227 patent also discloses different stacking methods of capacitors, please refer to Figures 4a, 4b, and 4c, which show a variety of different stacking methods of the icon of the patent, but no matter what the stacking method is, it is also the same as the above-mentioned U.S. No. 1 Patent No. US6249424 cannot overcome the disadvantages of easily damaged capacitors, complex manufacturing process, high cost and high short circuit rate

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