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High speed cam lookup using stored encoded key

A technology for addressing memory and keywords, applied in the field of high-speed access content addressable memory, which can solve the problems of low current carrying capacity, long duration, etc.

Inactive Publication Date: 2009-01-07
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the small transistor 106 has a lower current carrying capacity, it takes a longer duration to discharge the match line 102 in case of a data miscomparison

Method used

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  • High speed cam lookup using stored encoded key
  • High speed cam lookup using stored encoded key
  • High speed cam lookup using stored encoded key

Examples

Experimental program
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Embodiment Construction

[0017] figure 2 A functional block diagram of a representative processor 10 is depicted. Processor 10 executes instructions in instruction execution pipeline 12 according to control logic 14 . The pipeline includes various registers or latches 16 organized in pipeline stages and one or more arithmetic logic units (ALUs) 18 . A general purpose register (GPR) file 20 provides registers containing the top of the memory hierarchy.

[0018] The pipeline fetches instructions from an instruction cache (I-cache) 21 , which includes CAM 22 and RAM 23 . Instruction memory addressing and grants are managed by instruction side translation lookaside buffer (ITLB) 24 . Data is accessed from cache memory 25 including CAM 26 and RAM 27 . Data memory addressing and grants are managed by the main TLB 28 . In various embodiments, ITLB 24 may contain copies of portions of TLB 28 . Alternatively, ITLB 24 and TLB 28 may be integrated.

[0019] Additionally, processor 10 may include a micro-T...

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PUM

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Abstract

The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.

Description

technical field [0001] The present invention relates generally to the field of electronic circuits and more particularly to a method of high-speed accessing content addressable memory using an encoded key field and a stored encoded key. Background technique [0002] Microprocessors perform computing tasks in a wide variety of applications, including embedded applications such as portable electronic devices. The ever-expanding feature set and increased functionality of such devices requires even more computationally powerful processors. Accordingly, there is a need for processor improvements that increase execution speed. [0003] Most modern processors take advantage of the spatial and temporal locality properties of most programs by storing recently executed instructions and recently accessed data in one or more cache memories for ready access by the instruction execution pipeline. A cache is a high-speed, (usually) on-chip memory structure comprising random access memory...

Claims

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Application Information

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IPC IPC(8): G11C15/04
CPCG11C15/04G11C15/00G06F12/1027G06F2212/652
Inventor 杰弗里·赫伯特·费希尔迈克尔·泰坦·潘蔡贾名詹姆斯·诺里斯·迪芬德尔费尔
Owner QUALCOMM INC
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