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Pll circuit

A circuit and charge pump technology, applied in the direction of electrical components, automatic power control, etc., can solve the problem of not being able to control the output frequency at a certain value, leakage current, etc., and achieve the effect of good linearity and suppression of time changes.

Inactive Publication Date: 2012-07-25
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, in the above-mentioned conventional PLL circuit, in the locked state in which the output frequency of the output of the PLL circuit is substantially constant, the output portion of the loop filter 3 is in a high impedance state, and since the selection switch 64 is connected to this The output portion of the loop filter 3 in the high impedance state, therefore, it is judged that there is a problem that a weak current leaks from the output portion of the loop filter 3 in the high impedance state through the switch 64, and the weak leakage The output voltage of the above-mentioned loop filter 3 (the voltage of the input 67 of VCO4) changes due to the current, and the output frequency of the PLL circuit also changes with this change, and the output frequency cannot be controlled at a constant value with high precision.

Method used

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Embodiment approach 1

[0059] figure 1 It is a configuration diagram of a PLL circuit according to Embodiment 1 of the present invention.

[0060] exist figure 1 Among them, the PLL circuit is a phase comparator 1 that will detect the phase difference between the input signal 6 and the signal after the output frequency division of the VCO4 in the frequency division circuit 5, and provides the loop filter 3 with the phase difference obtained by the phase comparator 1. The charge pump circuit 2 for the charge corresponding to the detected phase difference signal, the loop filter 3 for smoothing the output signal of the charge pump circuit 2, the VCO4 for controlling the oscillation frequency by using the voltage of the loop filter 3, and the VCO4 for VCO4 The frequency dividing circuit 5 for dividing the output frequency is formed by connecting in a ring. Here, the VCO4 has two input terminals, two voltage-current conversion circuits 40 and 41 that convert the respective voltages of the two input ...

Embodiment approach 2

[0071] Hereinafter, a PLL circuit according to Embodiment 2 of the present invention will be described with reference to the drawings.

[0072] Figure 4 It is a configuration diagram of a PLL circuit according to Embodiment 2 of the present invention.

[0073] exist Figure 4 Herein, parts having the same structure as that of Embodiment 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0074] exist Figure 4 Among them, the difference from Embodiment 1 is that the voltage-current conversion circuits 40 and 41 are composed of an operational amplifier 52 that uses the input terminal of the voltage-current conversion circuit as an input signal on the negative side, and the gate terminal is connected to the output of the operational amplifier 52. , the PTr54 connecting the source terminal to the power supply, the drain terminal to the positive input terminal of the above-mentioned operational amplifier 52, the resistor 53 connected betwee...

Embodiment approach 3

[0077] Hereinafter, a PLL circuit according to Embodiment 3 of the present invention will be described with reference to the drawings.

[0078] Figure 5It is a configuration diagram of a PLL circuit according to Embodiment 3 of the present invention.

[0079] exist Figure 5 In , parts having the same configuration as those in Embodiment 2 are denoted by the same reference numerals, and descriptions thereof are omitted.

[0080] exist Figure 5 In the present invention, the difference from Embodiment 2 is that the input signal on the positive side of the operational amplifier 52 constituting the voltage-current conversion circuit 41, which receives the voltage of the loop filter 3 as an input, is used as a signal for monitoring the loop filter 3. Loop filter voltage monitor terminal 56 for voltage.

[0081] With the configuration as described above, it is possible to observe the potential of the loop filter during PLL operation without adding a new circuit.

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PUM

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Abstract

A PLL circuit includes a voltage-controlled oscillator (4), which has two voltage / current converting circuits (40,41) and a selecting circuit (42) for selecting an output of one of those voltage / current converting circuits (40,41). The output of the voltage / current converting circuit selected by the selecting circuit (42) is inputted to a current-controlled oscillator (45). The input side of the voltage / current converting circuit (41) is connected to the output side of a loop filter (3), while the input side of the other voltage / current converting circuit (40) is connected to an input terminal (8) used for evaluating the oscillation characteristic of the voltage-controlled oscillator (4). It is, therefore, achieved to effectively suppress both the temporal variation in output frequency ofthe PLL circuit and the temporal variation in voltage of the loop filter that would otherwise occur due to an arrangement in which the input terminal used for evaluating the oscillation characteristic of the voltage-controlled oscillator is connected to the loop filter via a switch.

Description

technical field [0001] The present invention relates to a PLL circuit (phase synchronization circuit) having a function of evaluating oscillation characteristics of a voltage-controlled oscillator. Background technique [0002] exist Figure 11 A conventional configuration diagram of a PLL circuit having an evaluation circuit of an oscillation characteristic of a voltage controlled oscillator (hereinafter referred to as VCO) is shown in . [0003] exist Figure 11 Among them, 1 is a phase comparator, 2 is a charge pump (charge pump) circuit, 3 is a loop filter, 4 is a voltage control oscillator (hereinafter referred to as VCO), 5 is a frequency division circuit, and 7 is a test control signal , 64, 65 are the switches controlled by the test control signal 7, 6 is the input signal, and 8 is the input control terminal of the VCO. A PLL circuit is formed by connecting a phase comparator 1, a charge pump circuit 2, a loop filter 3, a VCO 4, and a frequency dividing circuit 5 in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/099
CPCH03L2207/06H03L7/18H03L7/099H03L7/0896
Inventor 曾川和昭木下雅善山田祐嗣中塚淳二
Owner PANASONIC CORP
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