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Capacitive load driving circuit and plasma display panel

A load-driven, capacitive technology, applied in the direction of static indicators, instruments, etc., can solve the problem of not being able to control odd and even numbers at the same time, to expand the negative pulse width, improve yield and reliability, and absorb panels. The effect of deviation

Inactive Publication Date: 2009-04-01
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] However, in the structure of the second conventional example, odd and even control cannot be performed at the same time, and in order to adjust the pulse width arbitrarily, it is necessary to control the odd and even systems separately and mutually, and there are problems such as adjustment when the clock frequency changes. easy subject

Method used

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  • Capacitive load driving circuit and plasma display panel
  • Capacitive load driving circuit and plasma display panel
  • Capacitive load driving circuit and plasma display panel

Examples

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no. 1 approach

[0081] FIG. 1 is a diagram schematically showing the configuration of a PDP according to Embodiment 1 of the present invention. As shown in the figure, the PDP of this embodiment includes: a panel (display unit) 7; a plurality of data electrodes 4 arranged on the panel; a plurality of scan electrodes 5 intersecting the data electrodes 4; Erase / sustain electrode 6 provided for each scan electrode 5; scan driver 202 for driving scan electrode 5; data driver 1 for driving data electrode 4; erase / sustain driver 3 for driving erase / sustain electrode 6. Pulses having positive and negative polarities are applied to the scan electrodes 5 . In addition, components such as panel 7 , scan electrodes 5 , data electrodes 4 , and erase / sustain electrodes 6 formed on the panel serve as capacitive loads when viewed from a circuit drive unit such as scan drive unit 202 .

[0082] Scan data signal 8 , scan clock signal 9 , scan blanking signal 10 , and negative polarity pulse width control sig...

no. 2 approach

[0094] 6 is a block diagram showing the configuration of a scan drive unit (capacitive load drive circuit) according to a second embodiment of the present invention.

[0095] As shown in the figure, in the scan drive unit 350 of this embodiment, the high voltage output unit 13 of the scan drive unit 202 shown in FIG. Other configurations are the same as those of the scan drive unit 202 . The gain-variable high-voltage output block 300 is composed of a number of gain-variable high-voltage output units 301 corresponding to the scan electrodes. Each variable-gain high-voltage output unit 301 receives the output of the blanking unit 12 as an input, and supplies a signal to a corresponding scan electrode.

[0096] Next, a circuit configuration example and operation waveforms of the gain-variable high-voltage output unit 301 are shown using FIG. 7 . 7( a ) is a diagram showing a configuration example of the gain variable high voltage output unit 301 , and FIG. 7( b ) is a diagram ...

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Abstract

A capacitive load driving circuit and plasma display panel, wherein a scan driving section (202) includes: a shift register section (11) receiving a scan data signal (8) and a scan clock signal (9); a plurality of pulse width control circuits (211) each receiving an output signal from the shift register section (11) and a negative pulse width control signal (220) to output a signal whose pulse width is controlled based on the negative pulse width control signal (220); a blanking section (12) receiving the output signals from the plurality of pulse width control circuits and a blanking signal (10); and a plurality of high voltage output sections for amplifying the output signals from the plurality of pulse width control circuits (211), which are received via the blanking section (12), to successively output negative pulses each having a controlled pulse width to the scanning electrodes, such that a PDP capable of respectively regulating the width of the negative pulses applied to the scanning electrode corresponding to the rising of the clock frequency.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, and in particular, to a driver circuit for a multi-channel semiconductor integrated circuit for driving a capacitive load such as a plasma display. Background technique [0002] Embodiments of a capacitive load circuit for driving electrodes such as a plasma display panel (hereinafter referred to as PDP) will be described with reference to the drawings. [0003] FIG. 9 is a structural diagram of a general AC-type PDP. The conventional PDP shown in this figure includes: a panel 1007; a data electrode 1004 arranged on the panel 1007; a data drive unit 1001 for driving the data electrode 1004; an erasing / sustaining electrode 1006; Sustain drive unit 1003 ; scan electrode 1005 across panel 1007 ; scan drive unit 1002 for driving scan electrode 1005 ; and scan drive unit 1002 . The scan driving unit 1002 is controlled by a scan data signal 1008 , a scan clock signal 1009 and a scan blank...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/28G09G3/288G09G3/20G09G3/291G09G3/293G09G3/296G09G3/298
CPCG09G3/296G09G2310/066G09G3/2948G09G3/293G09G2330/028G09G2310/0218
Inventor 安藤仁吉田诚也松永弘树金田甚作
Owner PANASONIC CORP
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