Semiconductor non-volatile memory

Abstract

The invention provides a semiconductor non-volatile memory, wherein a memory cell can be read accurately without having to discharge bit lines before the read operation. When reading a memory cell, the first bit line connected to the drain thereof is connected to the voltage source to receive a predetermined voltage, and the second bit line connected to the source thereof is connected to the sense amplifier. In this process, the third bit line in the vicinity of the second bit line is connected to the ground power supply. Thus, since the third bit line in the vicinity of the second bit line being sensed is forcibly set to the ground level, no charge flows in therefrom, thus preventing a current flowing into the second bit line.

Description

technical field [0001] The present invention relates to semiconductor non-volatile memories, and more particularly to circuit structures involved in the readout of memory cells. Background technique [0002] Semiconductor non-volatile memories are getting smaller and larger. Among them, in high-speed applications, a VGA (Virtual Ground Architecture, virtual ground) type semiconductor nonvolatile memory, which is one of the NOR types, is often used in terms of integration. In this VGA type, memory cells are arranged without interruption between all bit lines, and adjacent memory cells share bit lines with each other, which can roughly realize the 4F 2 The refinement of the scaling law. [0003] However, in this VAG type, since adjacent memory cells share the bit line, by applying a drain voltage to the read memory cell (albeit slightly, by reading the source voltage of the memory cell), the Charges are successively accumulated on the bit lines on which the read memory cell...

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Problems solved by technology

Also, after that, it is necessary to continuously activate only the select gates required to read

[0024] That is, there is a problem that a discharge period for discharging each bit line to ground is necessary in the read operation.

In addition, there is a problem that the current consumption required to activate all the selection signals for the selected sector increases, and because the level of the selection signal is different, it is necessary to increase the problem of a booster circuit.

[0025] As described above, in the prior art, it is necessary to provide a period for each bit line in the discharge sector before the read operation of the memory cell, so this becomes a factor that hinders the speed-up of the system.

In addition, there is a problem that the current consumption of the circuit increases due to the discharge operation, and when the boost power supply is used for the discharge operation, there is a problem that the chip area increases due to the increase in the area of ​​the boost circuit.

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