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Field Programmable Gate Array

A gate array and capacitor technology, applied in static memory, instruments, logic circuits using basic logic circuit components, etc., can solve the problems of occupying FPGA chip area and excessive chip area, and achieve SRAM structure simplification, chip area reduction, The effect of miniaturization

Active Publication Date: 2011-12-07
CHENGDU SINO MICROELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this structure requires 6 MOS transistors, which occupy a large area of ​​the FPGA chip. Under the current situation that integrated circuits are increasingly pursuing high integration and miniaturization, the excessive occupation of the chip area is undoubtedly very unfavorable.

Method used

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Examples

Experimental program
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Embodiment Construction

[0021] see figure 2 .

[0022] The SRAM unit of this embodiment is composed of 2 MOS transmission transistors and 2 capacitors. The first capacitor C1 and the second capacitor C2 are used to store information. When the word line Z is active (high level), the first MOS transistor T1 And the second MOS transistor T2 is turned on, and the information on the bit line is transferred to the latch structure for storage until the word line Z is valid next time. But this structure only needs 2 MOS transistors, which can save a lot of FPGA chip area, thereby improving the integration level of the FPGA chip.

[0023] However, due to the slow discharge of the capacitor, the stored information may be lost, so an additional timing refresh circuit is required. Refresh the circuit schematic as Figure 5 shown.

[0024] The refresh circuit consists of a timing controller (essentially a cycle counter, the cycle value is an address number), an address generator (essentially a decoder, which...

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PUM

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Abstract

Field Programmable Gate Array, involving integrated circuit technology. The invention includes a SRAM unit and a refresh circuit, the SRAM unit is composed of a MOS tube and a capacitor, and the refresh circuit provides capacitance refresh for the SRAM unit. The beneficial effect of the present invention is that, since the SRAM structure of the present invention is greatly simplified compared with the prior art, the corresponding chip area can be greatly reduced, which is beneficial to the high integration and miniaturization of the chip.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] Compared with ASIC, FPGA (field programmable gate arrays) has two main advantages: 1. There is no NRE fee. 2, [0003] Shorter time to market. Therefore, FPGA has achieved great commercial success in the market. FPGA schematic diagram such as figure 1 . [0004] FPGA consists of the following parts: CLB, interconnect resources, IO. [0005] (1) Programmable logic block LB (Logic Block): It is the basic unit to realize user functions, and they are usually arranged in an array and scattered throughout the chip; [0006] (2) Programmable input and output block IO (Input / Output) cell: complete the interface between the logic on the chip and the external packaging pin, often surrounding the array around the chip; [0007] (3) Programmable interconnect resources IR (interconnection resources): They connect various programmable logic blocks or I / O blocks to fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/177G11C11/401G11C11/406
Inventor 李平李威李文昌
Owner CHENGDU SINO MICROELECTRONICS TECH CO LTD