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Hardware accelerated implementation process for bzip2 compression algorithm

A technology of hardware acceleration and implementation method, applied in the direction of electrical components, code conversion, concurrent instruction execution, etc., can solve the problems of limited use range, slow compression speed, etc., to achieve the effect of speeding up data compression, improving performance, and simplifying design

Inactive Publication Date: 2010-10-20
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Although the compression efficiency of bzip2 is higher than that of gzip or zip, its slower compression speed limits the scope of use

Method used

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  • Hardware accelerated implementation process for bzip2 compression algorithm
  • Hardware accelerated implementation process for bzip2 compression algorithm
  • Hardware accelerated implementation process for bzip2 compression algorithm

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Embodiment Construction

[0033] The specific implementation process of the hardware thread execution method based on the hybrid processor and FPGA architecture is as follows:

[0034] A method for implementing bzip2 compression algorithm hardware acceleration, the specific steps are as follows figure 1 Shown:

[0035] 1) The software manages the input and output of the accelerator

[0036] A hardware accelerator uses an input and output cache as a communication interface with a general-purpose computing system, and a general-purpose computing system refers to a general-purpose computer represented by a traditional desktop computer. The general-purpose computing system accesses the input and output cache of the hardware accelerator through the PCI-E bus. In the present invention, the input cache and the output cache are separated, and the input cache is called a local cache, which is used as the input data of the cache hardware accelerator, and the output cache is called a local storage. , used to st...

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Abstract

The invention discloses a hardware accelerating implementation method of a bzip2 compression algorithm, wherein, a hardware accelerator is utilized to implement preposing conversion and stroke length coding which cost a great deal of runtime so as to accelerate the program compression speed. The hardware accelerating implementation method has the characteristics as follows: firstly, an input / output buffer memory of the hardware accelerator is used as a communication interface, and is communicated with a general-purpose computing system through the communication interface; software prepares input data for the hardware accelerator and sorts and reads output data; and so the design of the hardware accelerator is simplified; and secondly, the preposing conversion and stroke length coding is realized in a hardware manner, a fully expanding 2048-bit parallel comparator and a shifter are adopted, so that the program execution is accelerated, the data compression speed of the bzip2 algorithm is accelerated, and the program performance is enhanced effectively.

Description

technical field [0001] The invention relates to the technical fields of software and hardware collaborative design and data compression, in particular to a method for realizing hardware acceleration of a bzip2 compression algorithm. Background technique [0002] With the application of new materials and the development of new technologies, VLSI technology has made great progress, which has laid a foundation for the development of multi-core processors (Chip Multi-Processor, CMP). CMP is to integrate multiple computing cores into one processor chip to improve computing power. According to whether the computing cores are equivalent or not, CMP can be divided into homogeneous multi-core and heterogeneous multi-core. [0003] In the next few years, the number of processing cores will increase. However, as the number of processing cores integrated in a single chip increases, it is difficult to increase the number of processing cores to bring greater performance improvement. Pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M7/30G06F9/38
Inventor 陈天洲严力科胡威王罡冯德贵吴斌斌陈度王勇刚刘敬伟
Owner ZHEJIANG UNIV
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