Clock synchronization circuit and operation method thereof

Abstract

A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase / frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase / frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase / frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application Nos. 10-2008-0002042 and 10-2008-0030293 filed on January 8, 2008 and April 1, 2008, respectively, which are incorporated by reference in their entirety into this article. technical field [0003] The present invention relates to semiconductor design technology, more specifically, to a clock synchronization circuit and its working method. Background technique [0004] Generally, in semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM), internal clock signals are generated using external clock signals and used as reference clock signals synchronized with various operation timings. Therefore, a clock synchronization circuit for synchronizing an external clock signal with an internal clock signal is provided in a semiconductor memory device. A typical clock synchronization circuit is a phase-locked loop (PLL). [0005] When ...

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Problems solved by technology

However, there is another problem that the periodically generated pattern jitter increases due to the ripple of the oscillation control voltage signal V_CTR

[0027] That is, in this PLL, there is a problem: when the resistance value of the resistor R is increased to eliminate the jitter peaking phenomenon, the pattern jitter of the oscillation control voltage signal V_CTR is largely caused; there is also another problem : When the resistance value of resistor R is reduced to eliminate pattern jitter, it causes jitter peaking

However, due to jitter peaking in the jitter transfer function of the phase-locked loop, a good filtering operation cannot be achieved

In addition, if the resistance value of the resistor R is adjusted so as to eliminate the jitter peaking phenomenon, the mode jitter of the oscillation control voltage signal V_CTR increases so that accurate phase / frequency locking operation cannot be achieved

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