Connection pad structure, chip joint structure and method for detecting chip joint state
A technology for detecting chip and bonding state, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor/solid-state device testing/measurement, etc. Insufficient space for display panel 1 and chip 3
Active Publication Date: 2009-08-26
AU OPTRONICS CORP
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Problems solved by technology
However, in the situation where the density of the circuit layout is constantly increasing, the space between the display panel 1 and the chip 3 will be insufficient, resulting in the contact between the conductive particles 7 and the lateral conduction, which will easily cause a short circuit 8
[0003] Recently, the technology of using non-conductive adhesive to bond chips and display panels has been proposed. However, due to the disadvantage that it is difficult to judge the bonding status of conductive bumps and bonding pads, its yield and reliability need to be further improved.
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[0041] In order for those skilled in the art to have a better understanding of the present invention, several preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, to describe in detail the composition and desired effects of the present invention.
[0042] Please refer to figure 2 and image 3 . figure 2 and image 3 is a schematic diagram of a chip bonding structure in a preferred embodiment of the present invention, wherein figure 2 For a top view diagram, image 3 for along figure 2 The sectional schematic diagram shown by the tangent line AA'. In order to clearly express the characteristics of the chip bonding structure of the display panel of the present invention, figure 2 The chip is not shown. In addition, each embodiment of the present invention takes the chip bonding structure of a display panel as an example, such as the chip bonding structure of various display panels such as a liquid crystal displ...
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The invention provides a connection pad structure, a chip joint structure and a method for detecting chip joint state. The chip joint structure comprises a light transmission substrate, a lighttight conductive layer, a insulation layer, a light transmission conductive layer, a chip and non-conductive glue. The lighttight conductive layer is arranged on the light transmission substrate and comprises at least a hole area; the insulation layer covers on the lighttight conductive layer, comprises an opening and substantially corresponds to the hole area of the lighttight conductive layer. The light transmission conductive layer is arranged on the insulation layer and is electrically connected with the lighttight conductive layer through the opening of the insulation layer, wherein the light transmission conductive layer, the insulation layer and the lighttight conductive layer form a light transmission area in the hole area; the chip comprises at least a conductive projection which is contacted and electrically connected with the light transmission conductive layer, wherein part of the surface of the projection forms a visual area by the light transmission area; and the non-conductive glue adheres the chip on the light transmission conductive layer. The invention can effectively improve yield rate and reliability of pressing technology for the chip.
Description
technical field [0001] The invention relates to a connection pad structure, a chip bonding structure and a method for detecting the chip bonding state, in particular to a connection pad structure with an opaque conductive layer designed with holes, and a method for directly and correctly detecting the chip bonding state method. Background technique [0002] COG (chip on glass) technology refers to the technology of bonding chips directly to the connection pads on the glass substrate. Due to the low cost of COG technology, it has been widely used in the chip bonding of display panels. The current COG technology mainly includes the use of metal welding and anisotropic conductive adhesive (ACF). Metal welding is to use low-melting point metals to weld the conductive bumps on the chip to the connection pads of the display panel. However, when the distance between conductive bumps is getting smaller and smaller, the COG technology using metal welding can no longer meet the deman...
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IPC IPC(8): H01L23/498H01L23/482H01L21/66H01L21/50
CPCH01L2224/13H01L2224/73204
Inventor 黄柏辅周诗频陈盈成石崇甫
Owner AU OPTRONICS CORP